Epson Apex 386/33 Canadian Product User Manual - Page 157

Smemr O -memri/o, Drq0-drq3 And Drq5-drq7 I, Dack0 To -dack3 And -dack5 To -dack7 0

Get Epson Apex 386/33 Canadian Product PDF manuals and user guides View all Epson Apex 386/33 Canadian Product manuals
Add to My Manuals
Save this manual to your list of manuals

Page 157 highlights

-SMEMR (O) -MEMR(I/O) These signals instruct the memory devices to drive data onto the data bus. "-SMEMR" is active only when the memory decode is within the low 1Mb of memory space. "-MEMR" is active on all memory read cycles. "-MEMR" may be driven by any microprocessor or DMA controller in the system. "-SMEMR" is derived from "MEMR" and the decode of the low 1 Mb of memory. When a microprocessor on the I/O channel wishes to drive "-MEMR", it must have the address lines valid on the bus for one system clock period before driving "-MEMR" active. Both signals are active LOW. -SMEMW (O) -MEMW (i/O) These signals instruct the memory devices to store the data present on the data bus. "-SMEMW" is active only when the memory decode is within the low 1Mb of the memory space. "-MEMW" is active on all memory read cycle. "-MEMW" may be driven by any microprocessor or DMA controller in the system. "SMEMW" is derived from "-MEMW" and the decode of the low 1 Mb of memory. When a microprocessor on the l/O channel wishes to drive "-MEMW", it must have the address lines valid on the bus for one system clock period before driving "-MEMW" active. Both signals are active low. DRQ0-DRQ3 and DRQ5-DRQ7 (I) DMA Requests 0 through 3 and 5 through 7 are asynchronous channel requests used by peripheral devices and the I/O channel micreprocessors to gain DMA service (or control of the system). They are prioritized, with "DRQ0" having the highest priority and "DRQ7" having the lowest. A request is generated by bringing a DRQ line to an active level. A DRQ line must be held high until the corresponding "DMA Request Acknowledge" (DACK) line goes active. "DRQ0" through "DRQ3" will perform El-bit DMA transfers; "DRQ5" through "DRQ7" will perform 16-bit transfers. "DRQ4" is used on the system board and is not available on the I/O channel. -DACK0 to -DACK3 and -DACK5 to -DACK7 (0) -DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests (DRQ0 through DRQ7). They are active low. 38 Chapter 6: Appendix

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
-SMEMR (O) -MEMR(I/O)
These signals instruct the memory devices to drive data onto the data
bus. “-SMEMR” is active only when the memory decode is within the
low 1Mb of memory space. “-MEMR” is active on all memory read
cycles. “-MEMR” may be driven by any microprocessor or DMA control-
ler in the system. “-SMEMR” is derived from “MEMR” and the decode
of the low 1 Mb of memory. When a microprocessor on the I/O channel
wishes to drive “-MEMR”, it must have the address lines valid on the
bus for one system clock period before driving “-MEMR” active. Both
signals are active LOW.
-SMEMW (O) -MEMW (i/O)
These signals instruct the memory devices to store the data present
on the data bus. “-SMEMW” is active only when the memory decode
is within the low 1Mb of the memory space. “-MEMW” is active on all
memory read cycle.
“-MEMW” may be driven by any microprocessor
or DMA controller in the system. “SMEMW” is derived from “-MEMW”
and the decode of the low 1 Mb of memory. When a microprocessor on
the l/O channel wishes to drive “-MEMW”, it must have the address
lines valid on the bus for one system clock period before driving
“-MEMW” active. Both signals are active low.
DRQ0-DRQ3 and DRQ5-DRQ7 (I)
DMA Requests 0 through 3 and 5 through 7 are asynchronous channel
requests used by peripheral devices and the I/O channel micreproces-
sors to gain DMA service (or control of the system). They are
prioritized, with “DRQ0” having the highest priority and “DRQ7” having
the lowest. A request is generated by bringing a DRQ line to an active
level. A DRQ line must be held high until the corresponding “DMA
Request Acknowledge” (DACK) line goes active. “DRQ0” through
“DRQ3” will perform El-bit DMA transfers; “DRQ5” through “DRQ7” will
perform 16-bit transfers. “DRQ4” is used on the system board and is
not available on the I/O channel.
-DACK0 to -DACK3 and -DACK5 to -DACK7 (0)
-DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA
requests (DRQ0 through DRQ7). They are active low.
38
Chapter 6: Appendix