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Fujitsu MHM2150AT Manual/User Guide - Page 64

Write circuit, Length Limited algorithm.

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4.6 Read/write Circuit 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC. The NRZ write data is converted from 16-bit data to 17-bit data by the encoder circuit then sent to the HDIC, and the data is written onto the media. (1) 16/17 MTR MEEPRML This device converts data using the 16/17 MTR (Maximum Transitions Run Length Limited) algorithm. This code is converted so that a maximum of three 1's are placed continuously and so that there are two or fewer 1's in a 17-bit border. (2) Write precompensation Write precompensation compensates, during a write process, for write nonlinearity generated at reading. Table 4.2 shows the write precompensation algorithm. Table 4.2 Write precompensation algorithm Bits 111001 111010 : 111111 000000 000001 : 010000 : 100000 Compensation -7 -6 -1 ±0 +1 +16 +32 C141-E104-03EN 4-11

Section	Page
Cover	1
Revision History	4
Preface	6
Important Alert Items	10
Manual Organization	12
Contents	14
Illustrations	19
CHAPTER 1 Device Overview	22
1.1 Features	23
1.1.1 Functions and performance	23
1.1.2 Adaptability	23
1.1.3 Interface	24
1.2 Device Specifications	25
1.2.1 Specifications summary	25
1.2.2 Model and product number	26
1.3 Power Requirements	26
1.4 Environmental Specifications	28
1.5 Acoustic Noise	29
1.6 Shock and Vibration	29
1.7 Reliability	30
1.8 Error Rate	31
1.9 Media Defects	31
CHAPTER 2 Device Configuration	32
2.1 Device Configuration	33
2.2 System Configuration	35
2.2.1 ATA interface	35
2.2.2 1 drive connection	35
2.2.3 2 drives connection	35
CHAPTER 3 Installation Conditions	38
3.1 Dimensions	39
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	49
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
CHAPTER 4 Theory of Device Operation	54
4.1 Outline	55
4.2 Subassemblies	55
4.2.1 Disk	55
4.2.2 Head	55
4.2.3 Spindle	56
4.2.4 Actuator	56
4.2.5 Air filter	56
4.3 Circuit Configuration	57
4.4 Power-on Sequence	60
4.5 Self-calibration	61
4.5.1 Self-calibration contents	61
4.5.2 Execution timing of self-calibration	62
4.5.3 Command processing during self-calibration	63
4.6 Read/write Circuit	63
4.6.1 Read/write preamplifier (HDIC)	63
4.6.2 Write circuit	64
4.6.3 Read circuit	66
4.6.4 Digital PLL circuit	67
4.7 Servo Control	68
4.7.1 Servo control circuit	68
4.7.2 Data-surface servo format	71
4.7.3 Servo frame format	73
4.7.4 Actuator motor control	74
4.7.5 Spindle motor control	75
CHAPTER 5 Interface	78
5.1 Physical Interface	79
5.1.1 Interface signals	79
5.1.2 Signal assignment on the connector	80
5.2 Logical Interface	83
5.2.1 I/O registers	84
5.2.2 Command block registers	85
5.2.3 Control block registers	90
5.3 Host Commands	90
5.3.1 Command code and parameters	91
5.3.2 Command descriptions	93
5.3.3 Error posting	160
5.4 Command Protocol	162
5.4.1 Data transferring commands from device to host	162
5.4.2 Data transferring commands from host to device	164
5.4.3 Commands without data transfer	166
5.4.4 Other commands	167
5.4.5 DMA data transfer commands	167
5.5 Ultra DMA Feature Set	169
5.5.1 Overview	169
5.5.2 Phases of operation	170
5.5.2.1 Ultra DMA burst initiation phase	170
5.5.2.2 Data transfer phase	171
5.5.2.3 Ultra DMA burst termination phase	171
5.5.3 Ultra DMA data in commands	172
5.5.3.1 Initiating an Ultra DMA data in burst	172
5.5.3.2 The data in transfer	173
5.5.3.3 Pausing an Ultra DMA data in burst	173
5.5.3.4 Terminating an Ultra DMA data in burst	174
5.5.4 Ultra DMA data out commands	177
5.5.4.1 Initiating an Ultra DMA data out burst	177
5.5.4.2 The data out transfer	177
5.5.4.3 Pausing an Ultra DMA data out burst	178
5.5.4.4 Terminating an Ultra DMA data out burst	179
5.5.5 Ultra DMA CRC rules	181
5.5.6 Series termination required for Ultra DMA	183
5.6 Timing	184
5.6.1 PIO data transfer	184
5.6.2 Multiword DMA data transfer	186
5.6.3 Transfer of Ultra DMA data	187
5.6.3.1 Starting of Ultra DMA data In Burst	187
5.6.3.2 Ultra DMA data burst timing requirements	188
5.6.3.3 Sustained Ultra DMA data in burst	190
5.6.3.4 Host pausing an Ultra DMA data in burst	191
5.6.3.5 Device terminating an Ultra DMA data in burst	192
5.6.3.6 Host terminating an Ultra DMA data in burst	193
5.6.3.7 Initiating an Ultra DMA data out burst	194
5.6.3.8 Sustained Ultra DMA data out burst	195
5.6.3.9 Device pausing an Ultra DMA data out burst	196
5.6.3.10 Host terminating an Ultra DMA data out burst	197
5.6.3.11 Device terminating an Ultra DMA data in burst	198
5.6.4 Power-on and reset	199
CHAPTER 6 Operations	200
6.1 Device Response to the Reset	201
6.1.1 Response to power-on	201
6.1.2 Response to hardware reset	203
6.1.3 Response to software reset	204
6.1.4 Response to diagnostic command	205
6.2 Address Translation	206
6.2.1 Default parameters	206
6.2.2 Logical address	207
6.3 Power Save	208
6.3.1 Power save mode	208
6.3.2 Power commands	210
6.4 Defect Management	210
6.4.1 Spare area	211
6.4.2 Alternating defective sectors	211
6.5 Read-Ahead Cache	213
6.5.1 Data buffer configuration	213
6.5.2 Caching operation	213
6.5.3 Usage of read segment	215
6.5.3.1 Mis-hit (no hit)	215
6.5.3.2 Sequential read	216
6.5.3.3 Full hit (hit all)	219
6.5.3.4 Partially hit	220
6.6 Write Cache	221
Glossary	224
Acronyms and Abbreviations	228