Hitachi DK23EA Specifications - Page 100

Device terminating an Ultra DMA Write

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DMARQ (device) Figure 6-17 Device terminating an Ultra DMA Write DMACK(host) tLI STOP (host) tRP DDMARDY- (device) tRFS tLI HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- tMLI tACK tIORDYZ tMLI tACK tCVS tCVH CRC tACK Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode 3(ns) Mode 4(ns) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6.7 10 CRC word valid setup time at sender tCVH 6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tRFS 75 70 60 60 60 50 Ready-to-final- STROBE time tRP 160 125 100 100 100 85 Ready-to-pause time tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times for DMACK_ K6602637 Rev.3 02.27.01 - 100 -

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K6602637
Rev.3
02.27.01
- 100 -
Figure 6-17 Device terminating an Ultra DMA Write
DMARQ
(device)
DMACK-
(host)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2,
CS0-, CS1-
t
ACK
t
MLI
t
CVS
t
LI
t
LI
t
ACK
CRC
t
CVH
t
ACK
t
IORDYZ
t
MLI
t
RP
t
RFS
Note:
The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect
after DMARQ and DMACK are negated.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode 3(ns) Mode 4(ns)
Mode5(ns)
Description
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
MIN
MAX
t
CVS
70
48
31
20
6.7
10
CRC word valid setup
time at sender
t
CVH
6.2
6.2
6.2
6.2
6.2
10
CRC word valid hold
time at sender
t
LI
0
150
0
150
0
150
0
100
0
100
0
75
Limited interlock time
t
MLI
20
20
20
20
20
20
Interlock
time
with
minimum
t
RFS
75
70
60
60
60
50
Ready-to-final-
STROBE time
t
RP
160
125
100
100
100
85
Ready-to-pause time
t
IORDYZ
20
20
20
20
20
20
Maximum time before
releasing IORDY
t
ACK
20
20
20
20
20
20
Setup and hold times
for DMACK_