Hitachi DK23EA Specifications - Page 28

Description of the Interface Signals

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6.2.3 Description of the Interface Signals The interface is an ATA(IDE) interface. Reserved pins should be left unconnected. The signal names and the pin numbers are shown in Figure 6-4 and Table 6.2. Table 6.2 shows signal definitions. "I" of I/O type represents an input signal from the device and "O" represents an output signal from the device. Signal name Pin RESET- 1 DD0-DD15 3-18 DIOW- 23 STOP *1 DIOR- 25 HDMARDY*1 HSTROBE *1 IORDY 27 DDMARDY*1 DSTROBE *1 CSEL 28 Table 6.2 Signal List(1/3) I/O type Description I This is a reset signal output from the host system and to be used for interface logic circuit. I/O This is a 16-bit bi-directional data bus. The lower 8 bits are used for register access other than data register. I The rising edge of this Write Strobe signal clocks data from the host data bus into a register on the device. Assertion of this signal by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst. I Activating this Read Strobe signal enables data from a register on the device to be clocked onto the host data bus. The rising edge of this signal latches data at the host. This signal is a flow control signal for Ultra DMA Read. Host asserts this signal, and indicates that the host is ready to receive Ultra DMA Read data . This signal is Write data strobe signal from the host for an Ultra DMA Write. Both the rising and falling edge latch the data from DD(15:0) into the device. O This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. This signal is a flow control signal for Ultra DMA Write. Device asserts this signal, and indicates that the device is ready to receive Ultra DMA Write data . This signal is the data in strobe signal from the device for an Ultra DMA Read. Both the rising and falling edge latch the data from DD(15:0) into the host. I This signal is used to configure a device as either DRIVE 0 or DRIVE1 when CSEL mode is selected. This signal is pulled up inside the drive. CSEL D rive address GND 0 OPEN 1 ççç*1: Signal name in Ultra DMA mode K6602637 Rev.3 02.27.01 - 28 -

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K6602637
Rev.3
02.27.01
- 28 -
6.2.3 Description of the Interface Signals
The interface is an ATA(IDE) interface. Reserved pins should be left unconnected. The signal names
and the pin numbers are shown in Figure 6-4 and Table 6.2. Table 6.2 shows signal definitions.
"I" of I/O type represents an input signal from the device and "O" represents an output signal from the
device.
Table 6.2
Signal List(1/3)
Signal name
Pin
I/O type
Description
RESET-
1
I
This is a reset signal output from the host system and to be
used for interface logic circuit.
DD0-DD15
3-18
I/O
This is a 16-bit bi-directional data bus. The lower 8 bits are
used for register access other than data register.
DIOW-
23
I
The rising edge of this Write Strobe signal clocks data from
the host data bus into a register on the device.
STOP
*1
Assertion of this signal by the host during an Ultra DMA burst
signals the termination of the Ultra DMA burst.
DIOR-
25
I
Activating this Read Strobe signal enables data from a register
on the device to be clocked onto the host data bus. The rising
edge of this signal latches data at the host.
HDMARDY-
*1
This signal is a flow control signal for Ultra DMA Read.
Host asserts this signal, and indicates that the host is ready to
receive Ultra DMA Read data .
HSTROBE
*1
This signal is Write data strobe signal from the host for an
Ultra DMA Write. Both the rising and falling edge latch
the data from DD(15:0) into the device.
IORDY
27
O
This signal is used to temporarily stop the host register access
(read or write) when the device is not ready to respond to a
data transfer request.
DDMARDY-
*1
This signal is a flow control signal for Ultra DMA Write. Device
asserts this signal, and indicates that the device is ready to
receive Ultra DMA Write data .
DSTROBE
*1
This signal is the data in strobe signal from the device for an
Ultra DMA Read. Both the rising and falling edge latch
the data from DD(15:0) into the host.
CSEL
28
I
This signal is used to configure a device as either DRIVE 0 or
DRIVE1 when CSEL mode is selected.
This signal is pulled up inside the drive.
CSEL
GND
OPEN
0
1
Drive address
*1
: Signal name in Ultra DMA mode