Hitachi DK23EA Specifications - Page 95

Symbol Min Max Min Max Min Max Min Max Min Max Min Max - 60 driver

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Figure 6-12 Host terminating an Ultra DMA Read DMARQ (device) DMACK(host) STOP (host) HDMARDY(host) DSTROBE (device) tRP tRFS tLI tAZ tMLI tZAH tMLI tLI tACK tACK tIO R D Y Z D D (1 5 :0 ) tCVS CRC tCVH tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode3(ns) Mode4(ns) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6.7 10 CRC word valid setup time at sender tCVH 6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for output drivers turning on tRFS 75 70 60 60 60 50 Ready-to-final-STROBE time tRP 160 125 100 100 100 85 Ready-to-pause time tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times before assertion and negation of DMACK_ K6602637 Rev.3 02.27.01 - 95 -

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K6602637
Rev.3
02.27.01
- 95 -
Figure 6-12 Host terminating an Ultra DMA Read
t
CVH
CRC
t
AZ
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
DA0, DA1, DA2,
CS0-, CS1-
t
ACK
t
MLI
t
LI
t
LI
t
IORDYZ
t
ACK
t
ACK
t
ZAH
t
MLI
t
CVS
t
RFS
t
RP
Note:
The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
Mode 0(ns) Mode 1(ns) Mode 2(ns)
Mode3(ns) Mode4(ns) Mode5(ns)
Description
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t
CVS
70
48
31
20
6.7
10
CRC
word valid setup time
at sender
t
CVH
6.2
6.2
6.2
6.2
6.2
10
CRC word valid hold time at
sender
t
LI
0
150
0
150
0
150
0
100
0
100
0
75
Limited interlock time
t
MLI
20
20
20
20
20
20
Interlock time with minimum
t
AZ
10
10
10
10
10
10
Maximum time allowed for
output drivers to release
t
ZAH
20
20
20
20
20
20
Minimum delay time for
output drivers turning on
t
RFS
75
70
60
60
60
50
Ready-to-final-STROBE
time
t
RP
160
125
100
100
100
85
Ready-to-pause time
t
IORDYZ
20
20
20
20
20
20
Maximum time before
releasing IORDY
t
ACK
20
20
20
20
20
20
Setup and hold times before
assertion and negation of
DMACK_