Intel E5472 Data Sheet

Intel E5472 - Cpu Xeon Quad Core 3.00Ghz Fsb1600Mhz 12M Lga771 Tray Manual

Get Intel E5472 - Cpu Xeon Quad Core 3.00Ghz Fsb1600Mhz 12M Lga771 Tray PDF manuals and user guides
UPC - 735858200684
View all Intel E5472 manuals
Add to My Manuals
Save this manual to your list of manuals

Intel E5472 manual content summary:

  • Intel E5472 | Data Sheet - Page 1
    Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008 318589-005
  • Intel E5472 | Data Sheet - Page 2
    to them. The Quad-Core Intel® Xeon® Processor 5400 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 64-bit computing on Intel architecture requires a computer
  • Intel E5472 | Data Sheet - Page 3
    Package Insertion Specifications 48 3.6 Processor Mass Specifications 48 3.7 Processor Materials 48 3.8 Processor Markings 48 3.9 Processor Land Coordinates 49 4 Land Listing...51 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments 51 4.1.1 Land Listing by Land Name 51 4.1.2 Land
  • Intel E5472 | Data Sheet - Page 4
    Tools Specifications 117 9.1 Debug Port System Requirements 117 9.2 Target System Implementation 117 9.2.1 System Implementation 117 9.3 Logic Analyzer Interface (LAI 117 9.3.1 Mechanical Considerations 118 9.3.2 Electrical Considerations 118 4 Quad-Core Intel® Xeon® Processor 5400 Series
  • Intel E5472 | Data Sheet - Page 5
    View 50 6-1 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile ......... 81 6-2 Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profiles A and B 83 6-3 Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile 86 6-4 Quad-Core Intel® Xeon® Processor L5400 Series
  • Intel E5472 | Data Sheet - Page 6
    by Land Name 51 4-2 Land Listing by Land Number 61 5-1 Signal Definitions 71 6-1 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step) Thermal Specifications ...81 6-2 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table .82 6-3 Quad-Core Intel® Xeon® Processor X5400
  • Intel E5472 | Data Sheet - Page 7
    version 004. Denoted in the Introduction section that E-step of the X5482 falls into the 120W X5400 family. Added X5492 processor to Table 7-1 and in Introduction section. § Date November 2007 March 2008 April 2008 August 2008 August 2008 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 7
  • Intel E5472 | Data Sheet - Page 8
    8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
  • Intel E5472 | Data Sheet - Page 9
    on Intel® 64 Architecture and its programming model can be found in the Intel® 64 and IA-32 Architectures Software Developer's Manual, at http://www.intel.com/products/processor/manuals/. In addition, the Quad-Core Intel® Xeon® Processor 5400 Series supports the Execute Disable Bit functionality
  • Intel E5472 | Data Sheet - Page 10
    /virtualization/index.htm. The Quad-Core Intel® Xeon® Processor 5400 Series is intended for high performance server and workstation systems. The Quad-Core Intel® Xeon® Processor 5400 Series supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets
  • Intel E5472 | Data Sheet - Page 11
    Intel® Xeon® Processor 5400 Series. For this document "Quad-Core Intel® Xeon® Processor L5400 Series" is used to call out specifications that are unique to the Quad-Core Intel® Xeon® Processor L5400 Series SKU. • Quad-Core Intel® Xeon® Processor L5408 - Intel 64-bit microprocessor intended for dual
  • Intel E5472 | Data Sheet - Page 12
    processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) - Estimate of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods. Actual specifications
  • Intel E5472 | Data Sheet - Page 13
    3A Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B Intel® 64 and IA-32 Intel® Architectures Optimization Reference Manual Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual Documentation Changes Quad-Core Intel® Xeon® Processor 5400 Series Specification
  • Intel E5472 | Data Sheet - Page 14
    14
  • Intel E5472 | Data Sheet - Page 15
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® Xeon® Processor 5400 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling
  • Intel E5472 | Data Sheet - Page 16
    specifications outlined in Table 2-12. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Quad-Core Intel® Xeon® Processor sized to meet the expected load. To insure optimal performance, various factors associated with the power delivery solution must be
  • Intel E5472 | Data Sheet - Page 17
    are not necessarily committed production frequencies. 3. For valid processor core frequencies, see Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. 4. The lowest bus ratio supported by the Quad-Core Intel® Xeon® Processor 5400 Series is 1/6. 2.4.1 Front Side Bus Frequency Select
  • Intel E5472 | Data Sheet - Page 18
    appropriate platform design guidelines for decoupling and routing guidelines. Voltage Identification (VID) The Voltage Identification (VID) specification for the Quad-Core Intel® Xeon® Processor 5400 Series is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD
  • Intel E5472 | Data Sheet - Page 19
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should
  • Intel E5472 | Data Sheet - Page 20
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 1 1 0 0 1 1 0.9750 64 1 1 0 0 1 0 0.9875 processor to remain within its specifications 4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code
  • Intel E5472 | Data Sheet - Page 21
    Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 0 0 1 1 LL_ID0 0 1 0 1 Description Reserved Dual-Core Intel® Xeon® Processor 5100 series, Dual-Core Intel® Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon® Processor 5400 Series Reserved Quad-Core Intel® Xeon
  • Intel E5472 | Data Sheet - Page 22
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI10 - cannot be grouped with
  • Intel E5472 | Data Sheet - Page 23
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group CMOS Asynchronous Output FSB Clock TAP Input TAP Output Power/Other Type Asynchronous Clock Synchronous to TCK
  • Intel E5472 | Data Sheet - Page 24
    Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The Quad-Core Intel® Xeon® Processor 5400 Series contains Digital Thermal
  • Intel E5472 | Data Sheet - Page 25
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Maximum
  • Intel E5472 | Data Sheet - Page 26
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.11 Note: 2.12 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache
  • Intel E5472 | Data Sheet - Page 27
    Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not
  • Intel E5472 | Data Sheet - Page 28
    steps FSB termination voltage (DC + AC specification) PLL supply voltage (DC + AC specification) ICC for Quad-Core Intel® Xeon® Processor X5482 with multiple VID Launch - FMB ICC for Quad-Core Intel® Xeon® Processor X5400 Series with multiple VID Launch - FMB ICC for Quad-Core Intel® Xeon® Processor
  • Intel E5472 | Data Sheet - Page 29
    2-12. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter ITT ICC_TDC ICC_TDC ICC_TDC ICC_TDC ICC_TDC ICC_VTT_OUT ICC_GTLREF ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable Thermal Design Current (TDC) Quad-Core Intel® Xeon® Processor X5482 Launch - FMB
  • Intel E5472 | Data Sheet - Page 30
    at 1.1 V. 17. ICC_RESET is specified while PWRGOOD and RESET# are asserted. 18. The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only. Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time Sustained Current (A) 16 0 15 5 15 0 14 5 14 0 13
  • Intel E5472 | Data Sheet - Page 31
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-3. Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time Sustained Current (A) 13 0 12 5 12 0 115 110 10 5 10 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or
  • Intel E5472 | Data Sheet - Page 32
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-5. Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time 70 Sustained Current (A) 65 60 55 50 45 40 0 .0 1 0 .1 1 10 Time Duration (s) 10 0 10 0 0 Notes: 1. Processor or Voltage
  • Intel E5472 | Data Sheet - Page 33
    Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. Table 2-14. Quad-Core Intel® Xeon® Processor X5400 Series, Quad-Core Intel® Xeon® Processor E5400 Series, Quad-Core Intel® Xeon® Processor L5400
  • Intel E5472 | Data Sheet - Page 34
    (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation. 4. ICC values greater than 102A are not applicable for the Quad-Core Intel® Xeon® Processor E5400 Series. 5. ICC values greater
  • Intel E5472 | Data Sheet - Page 35
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-7. Quad-Core Intel® Xeon® Processor X5482 VCC Static and Transient Tolerance Load Lines 0 VID - 0.000 Icc [A] 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
  • Intel E5472 | Data Sheet - Page 36
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-8. Quad-Core Intel® Xeon® Processor 0.160 VCC Minimum VCC Typical VID - 0.180 VID - 0.200 Figure 2-9. Quad-Core Intel® Xeon® Processor E5400 Series VCC Static and Transient Tolerance Load Lines Vcc [V] 0 VID - 0.
  • Intel E5472 | Data Sheet - Page 37
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-10. Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient Tolerance Load Lines 0 VID - 0.000 Icc [A] 5 10 15 20 25 30 35 40 45 50 55 60 VID - 0.020
  • Intel E5472 | Data Sheet - Page 38
    by value of the external pullup resistor to VTT. Refer to platform design guide for details. 4. For VIN between 0 V and VOH. 2.13.2 VCC Overshoot Specification The Quad-Core Intel® Xeon® Processor 5400 Series can tolerate short transient overshoot events where VCC exceeds the VID voltage
  • Intel E5472 | Data Sheet - Page 39
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-11. VCC Overshoot Example Waveform processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported
  • Intel E5472 | Data Sheet - Page 40
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate
  • Intel E5472 | Data Sheet - Page 41
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 7. Threshold Region is defined as a region entered around . 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent and
  • Intel E5472 | Data Sheet - Page 42
    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-14. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670
  • Intel E5472 | Data Sheet - Page 43
    Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771
  • Intel E5472 | Data Sheet - Page 44
    Mechanical Specifications Figure 3-2. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3) Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution are available in the processor Thermal/Mechanical Design
  • Intel E5472 | Data Sheet - Page 45
    Mechanical Specifications Figure 3-3. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3) 45
  • Intel E5472 | Data Sheet - Page 46
    Mechanical Specifications Figure 3-4. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 3 of 3) Note: The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial processors. 46
  • Intel E5472 | Data Sheet - Page 47
    N lbf me Notes 1,2,3,9 1,3,4,5,6 1,3,7,8 Notes: 1. These specifications apply to uniform compressive loading in a direction perpendicular to the Intel® components using 771-land LGA package that interfaces with the motherboard via a LGA771 socket. 9. Refer to the Quad-Core Intel® Xeon® Processor
  • Intel E5472 | Data Sheet - Page 48
    Insertion Specifications The Quad-Core Intel® Xeon® Processor 5400 Series can be inserted and removed 15 times from an LGA771 socket, which meets the criteria outlined in the LGA771 Socket Design Guidelines. 3.6 Processor Mass Specifications The typical mass of the Quad-Core Intel® Xeon® Processor
  • Intel E5472 | Data Sheet - Page 49
    Mechanical Specifications Figure 3-5. Processor Top-side Markings (Example) GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Legend: GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Mark Text (Production Mark): 3200DP/12M/1600 Intel ® Xeon ® Proc# SXXX COO i (M) © '07 FPO
  • Intel E5472 | Data Sheet - Page 50
    Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View AN AM AL AK AJ AH AG AF AE AD AC AB AA Address / 25 26 27 28 29 30 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y Socket 771 W V Quadrants U T Bottom View R P N M L K J H G F E D
  • Intel E5472 | Data Sheet - Page 51
    Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by
  • Intel E5472 | Data Sheet - Page 52
    Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Table 4-1. Land Listing by Land Name (Sheet 4 of 20) Pin Name D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55
  • Intel E5472 | Data Sheet - Page 53
    Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Table 4-1. Land Listing by Land Name (Sheet 6 of 20) Pin Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
  • Intel E5472 | Data Sheet - Page 54
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 7 of 20) Pin Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET Input Input Input Output Input Input Input Table 4-1. Land Listing by Land Name (Sheet 8 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel E5472 | Data Sheet - Page 55
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Listing by Land Name (Sheet 10 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel E5472 | Data Sheet - Page 56
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 11 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Listing by Land Name (Sheet 12 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
  • Intel E5472 | Data Sheet - Page 57
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 20) Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC Output Input Output Output Output Output Output Output Output Table 4-1. Land Listing by Land Name (Sheet 14 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel E5472 | Data Sheet - Page 58
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Listing by Land Name (Sheet 16 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel E5472 | Data Sheet - Page 59
    Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Listing by Land Name (Sheet 18 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
  • Intel E5472 | Data Sheet - Page 60
    /Other V27 Power/Other V28 Power/Other V29 Power/Other V3 Power/Other V30 Power/Other Direction Table 4-1. Land Listing by Land Name (Sheet 20 of 20) Pin Name VSS VSS VSS VSS VSS VSS VSS VSS_DIE_SENSE VSS_DIE_SENSE2 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
  • Intel E5472 | Data Sheet - Page 61
    Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. Pin Name A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 Input/Output Table 4-2. Land Listing by Land Number (Sheet 2 of 20) Pin No. Pin Name AA7 AA8 AB1 AB2 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB3 AB30 AB4 AB5 AB6 AB7 AB8
  • Intel E5472 | Data Sheet - Page 62
    Listing by Land Number (Sheet 3 of 20) Pin No. Pin Name AD26 AD27 AD28 AD29 AD3 AD30 AD4 AD5 AD6 AD7 AD8 AE1 AE10 Power/Other Output Table 4-2. Land Listing by Land Number (Sheet 4 of 20) Pin No. Pin Name AE9 AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF2 AF20 AF21 AF22 AF23 AF24
  • Intel E5472 | Data Sheet - Page 63
    Listing by Land Number (Sheet 5 of 20) Pin No. Pin Name AG18 AG19 AG2 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 Other Power/Other Table 4-2. Land Listing by Land Number (Sheet 6 of 20) Pin No. Pin Name AH27 AH28 AH29 AH3 AH30 AH4 AH5 AH6 AH7 AH8 AH9 AJ1 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15
  • Intel E5472 | Data Sheet - Page 64
    Power/Other Power/Other Power/Other Table 4-2. Land Listing by Land Number (Sheet 8 of 20) Pin No. Pin Name AL18 AL19 AL2 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL3 AL30 AL4 AL5 AL6 AL7 AL8 AL9 AM1 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 64
  • Intel E5472 | Data Sheet - Page 65
    Listing by Land Number (Sheet 9 of 20) Pin No. Pin Name AM26 AM27 AM28 AM29 AM3 AM30 AM4 AM5 AM6 AM7 AM8 AM9 Power/Other Output Table 4-2. Land Listing by Land Number (Sheet 10 of 20) Pin No. Pin Name B10 D10# B11 VSS B12 D13# B13 RESERVED B14 VSS B15 D53# B16 D55# B17 VSS B18
  • Intel E5472 | Data Sheet - Page 66
    4-2. Land Listing by Land Number (Sheet 11 of 20) Pin No. Pin Name C2 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C3 C30 C4 C5 /Output Input/Output Input Table 4-2. Land Listing by Land Number (Sheet 12 of 20) Pin No. Pin Name D29 D3 D30 D4 D5 D6 D7 D8 D9 E1 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19
  • Intel E5472 | Data Sheet - Page 67
    Listing by Land Number (Sheet 13 of 20) Pin No. Pin Name Signal Buffer Type Direction F10 F11 F12 F13 F14 F15 F16 F17 F18 Input/Output Table 4-2. Land Listing by Land Number (Sheet 14 of 20) Pin No. Pin Name Signal Buffer Type Direction G19 G2 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G3 G30
  • Intel E5472 | Data Sheet - Page 68
    4-2. Land Listing by Land Number (Sheet 15 of 20) Pin No. Pin Name H27 H28 H29 H3 H30 H4 H5 H6 H7 H8 H9 J1 J10 J11 J12 Other Input/Output Input/Output Table 4-2. Land Listing by Land Number (Sheet 16 of 20) Pin No. Pin Name J9 K1 K2 K23 K24 K25 K26 K27 K28 K29 K3 K30 K4 K5 K6 K7 K8 L1 L2 L23
  • Intel E5472 | Data Sheet - Page 69
    4-2. Land Listing by Land Number (Sheet 17 of 20) Pin No. Pin Name M28 M29 M3 M30 M4 M5 M6 M7 M8 N1 N2 N23 N24 N25 N26 Input Input/Output Input/Output Table 4-2. Land Listing by Land Number (Sheet 18 of 20) Pin No. Pin Name P8 R1 R2 R23 R24 R25 R26 R27 R28 R29 R3 R30 R4 R5 R6 R7 R8 T1 T2 T23
  • Intel E5472 | Data Sheet - Page 70
    Land Listing by Land Number (Sheet 19 of 20) Pin No. Pin Name U28 U29 U3 U30 U4 U5 U6 U7 U8 V1 V2 V23 V24 Output Input/Output Table 4-2. Land Listing by Land Number (Sheet 20 of 20) Pin No. Pin Name W8 VCC Y1 RESERVED Y2 VSS Y23 VCC Y24 VCC Y25 VCC Y26 VCC Y27 VCC Y28 VCC Y29
  • Intel E5472 | Data Sheet - Page 71
    Name processor masks 2 physical address bit processor's address wrap- around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction Quad-Core Intel® Xeon® Processor
  • Intel E5472 | Data Sheet - Page 72
    BINIT# as appropriate to the error handling architecture of the system. I/O BNR# ( drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. I/O BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance 2 O monitor signals. They are outputs from the processor
  • Intel E5472 | Data Sheet - Page 73
    64-bit 3 data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad noconnect on the Quad-Core Intel® Xeon® Processor 5400 Series package. DBR# is not a processor signal. I/O
  • Intel E5472 | Data Sheet - Page 74
    to Vol. 3 of the Intel® 64 and IA-32 Architectures Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. I The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to
  • Intel E5472 | Data Sheet - Page 75
    instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit the signals of those names on the Pentium® processor. Both signals are asynchronous
  • Intel E5472 | Data Sheet - Page 76
    Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3. O These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. These signals are not connected to the processor die. Both the bits specifications
  • Intel E5472 | Data Sheet - Page 77
    In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. I TESTHI[12:10] must be connected to
  • Intel E5472 | Data Sheet - Page 78
    to VTT on the motherboard. O The VTT_SEL signal is used to select the correct VTT voltage level for the processor. VTT_SEL is connected to VSS on the Quad-Core Intel® Xeon® Processor 5400 Series package. Notes: 1. For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the
  • Intel E5472 | Data Sheet - Page 79
    (TCASE) specifications as defined by the applicable thermal profile (see Table 6-1 and Figure 6-1 for the Quad-Core Intel® Xeon® Processor X5482, Table 6-3 and Figure 6-2 for the Quad-Core Intel® Xeon® Processor X5400 Series, Table 6-6 and Figure 6-3 for the Quad-Core Intel® Xeon® Processor E5400
  • Intel E5472 | Data Sheet - Page 80
    either thermal profile should result in virtually no TCC activation. Refer to the Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines (TMDG). The Quad-Core Intel® Xeon® Processor X5400 Series supports a dual Thermal Profile, either of which can
  • Intel E5472 | Data Sheet - Page 81
    or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. 6. The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only. Figure 6-1. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile
  • Intel E5472 | Data Sheet - Page 82
    Thermal Specifications Table 6-2. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table Power (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110
  • Intel E5472 | Data Sheet - Page 83
    activation and measurable performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile B do not meet the processor's thermal specifications and may result in permanent damage to the processor. 5. Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal
  • Intel E5472 | Data Sheet - Page 84
    Thermal Specifications Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table Power (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
  • Intel E5472 | Data Sheet - Page 85
    are based on silicon characterization. 4. Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor E5400 Series may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting
  • Intel E5472 | Data Sheet - Page 86
    the Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss
  • Intel E5472 | Data Sheet - Page 87
    in a future release of this document. 4. Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor L5400 Series may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all
  • Intel E5472 | Data Sheet - Page 88
    in a future release of this document. 4. Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor L5408 may be shipped under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned
  • Intel E5472 | Data Sheet - Page 89
    of the Quad-Core Intel® Xeon® Processor L5408 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss
  • Intel E5472 | Data Sheet - Page 90
    Features Quad-Core Intel® Xeon® Processor 5400 Series provides two thermal monitor features, Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2. The Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications. When
  • Intel E5472 | Data Sheet - Page 91
    will support Intel® Thermal Monitor 2 will be provided in future releases of the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) when available. For more details also refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual. When Intel
  • Intel E5472 | Data Sheet - Page 92
    Thermal Specifications The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the Quad-Core Intel® Xeon® Processor 5400 Series). When the TCC is activated, the processor
  • Intel E5472 | Data Sheet - Page 93
    solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TCASE, or PROCHOT#. FORCEPR# Signal The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the
  • Intel E5472 | Data Sheet - Page 94
    to 2Mbps). The PECI interface on the Quad-Core Intel® Xeon® Processor 5400 Series is disabled by default and must be enabled through BIOS. Figure 6-8. Quad-Core Intel® Xeon® Processor 5400 Series PECI Topology P ro c es s o r (Socket 0) 0 x 3 D om ain0 G5 0 0 x 3 D om ain1 0 PECI Host
  • Intel E5472 | Data Sheet - Page 95
    sample rate, whether the temperature filter is enabled, how often the PECI host will poll the processor for temperature data, and the rate at which fan speed is changed. Depending on the designer's specific requirements the DTS sample rate and alpha-beta filter may have no effect on the fan control
  • Intel E5472 | Data Sheet - Page 96
    implement an alert to software in the event of a critical or continuous fault condition. 6.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed in Table 6-12 below: Table 6-12. GetTemp0() GetTemp1()Error
  • Intel E5472 | Data Sheet - Page 97
    -Core Intel® Xeon® Processor 5400 Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package. 7.2 Clock Control and Low Power States The Quad-Core Intel® Xeon® Processor 5400 Series supports
  • Intel E5472 | Data Sheet - Page 98
    its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction. When one of the processor cores execute the HALT or MWAIT instruction, that processor
  • Intel E5472 | Data Sheet - Page 99
    PEXTENDED_HALT Quad-Core Intel® Xeon® Processor L5408 Extended HALT State Power Extended HALT State Power Extended HALT State Power Extended HALT State Power Typ Max 16 Unit W Notes 1 2 16 W 2 16/20 W 2,3 12 W 2 12 W 4 Notes: 1. Processors running in the lowest bus ratio supported
  • Intel E5472 | Data Sheet - Page 100
    Service snoops to caches 7.2.3 100 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon
  • Intel E5472 | Data Sheet - Page 101
    ® 64 and IA-32 Architectures Software Developer's Manual. Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in the Quad-Core Intel® Xeon® Processor
  • Intel E5472 | Data Sheet - Page 102
    by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Quad-Core Intel® Xeon® Processor 5400 Series has hardware logic that coordinates
  • Intel E5472 | Data Sheet - Page 103
    Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Quad-Core Intel® Xeon® Processor 5400 Series will be offered as an Intel boxed
  • Intel E5472 | Data Sheet - Page 104
    Boxed Processor Specifications Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink 104
  • Intel E5472 | Data Sheet - Page 105
    Boxed Processor Specifications Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5400 Series Thermal Solution (Exploded View) 8.2 8.2.1 Notes: 1. The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. The screws,
  • Intel E5472 | Data Sheet - Page 106
    Figure 8-4. Top Side Board Keepout Zones (Part 1) Boxed Processor Specifications 106
  • Intel E5472 | Data Sheet - Page 107
    Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2) 107
  • Intel E5472 | Data Sheet - Page 108
    Figure 8-6. Bottom Side Board Keepout Zones Boxed Processor Specifications 108
  • Intel E5472 | Data Sheet - Page 109
    Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones 109
  • Intel E5472 | Data Sheet - Page 110
    Figure 8-8. Volumetric Height Keep-Ins Boxed Processor Specifications 110
  • Intel E5472 | Data Sheet - Page 111
    Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink) 111
  • Intel E5472 | Data Sheet - Page 112
    Boxed Processor Specifications Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink) 112
  • Intel E5472 | Data Sheet - Page 113
    to support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB 3.6, TEB 2.1 or CEB 1.1). These specification can active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing
  • Intel E5472 | Data Sheet - Page 114
    itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution Description PWM Control Frequency Range Min Frequency 21,000 Nominal Frequency 25,000
  • Intel E5472 | Data Sheet - Page 115
    problems related to shock and vibration. The board must not bend beyond specification in order to avoid damage. The boxed processor contains the components necessary to solve both issues. The boxed processor will include the following items: • Quad-Core Intel® Xeon® Processor manual • Intel Inside
  • Intel E5472 | Data Sheet - Page 116
    Boxed Processor Specifications § 116
  • Intel E5472 | Data Sheet - Page 117
    logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Quad-Core Intel® Xeon® Processor 5400 Series systems. Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces. The following information is general in nature
  • Intel E5472 | Data Sheet - Page 118
    Specifications 9.3.1 9.3.2 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket Considerations The LAI will also affect the electrical performance of the FSB, therefore it is critical to
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
318589-005
Quad-Core Intel® Xeon® Processor
5400 Series
Datasheet
August 2008