Intel E5472 Data Sheet - Page 78

Signal Definitions

78

Notes:

1.

For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of

symmetric agents is one. Maximum number of priority agents is zero.

2.


symmetric agents is two. Maximum number of priority agents is zero.

3.


symmetric agents is two. Maximum number of priority agents is one.

§

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by

debug tools.

See the

Debug Port Design Guide for Intel

®

5000 Series Chipset

Memory Controller Hub (MCH) Systems (External Version)

for further

information.

TRDY#

I

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of all FSB agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

V

CCPLL

I

The Quad-Core Intel® Xeon® Processor 5400 Series implements an

on-die PLL filter solution. The V

CCPLL

input is used as a PLL supply

voltage.

VCC_DIE_SENSE

VCC_DIE_SENSE2

O

VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low

impedance connection to the processor core power and ground. This

signal should be connected to the voltage regulator feedback signal,

which insures the output voltage (that is, processor voltage) remains

within specification. Please see the applicable platform design guide

for implementation details.

VID[6:1]

O

VID[6:1] (Voltage ID) pins are used to support automatic selection of

power supply voltages (V

CC

). These are CMOS signals that are driven

by the processor and must be pulled up through a resistor.

Conversely, the voltage regulator output must be disabled prior to the

voltage supply for these pins becomes invalid. The VID pins are

needed to support processor voltage specification variations. See

Table 2-4

for definitions of these pins. The VR must supply the

voltage that is requested by these pins, or disable itself.

VID_SELECT

O

VID_SELECT is an output from the processor which selects the

appropriate VID table for the Voltage Regulator. This signal is not

connected to the processor die. This signal is a no-connect on the

Quad-Core Intel® Xeon® Processor 5400 Series package.

VSS_DIE_SENSE

VSS_DIE_SENSE2

O

VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low

impedance connection to the processor core power and ground. This

signal should be connected to the voltage regulator feedback signal,

which insures the output voltage (that is, processor voltage) remains

within specification. Please see the applicable platform design guide

for implementation details.

VTT

P

The FSB termination voltage input pins. Refer to

Table 2-12

for

further details.

VTT_OUT

O

The VTT_OUT signals are included in order to provide a local V

TT

for

some signals that require termination to V

TT

on the motherboard.

VTT_SEL

O

The VTT_SEL signal is used to select the correct V

TT

voltage level for

the processor. VTT_SEL is connected to VSS on the Quad-Core Intel®

Xeon® Processor 5400 Series package.

Table 5-1.

Signal Definitions (Sheet 8 of 8)

Name

Type

Description

Notes

Section	Page
Quad-Core Intel® Xeon® Processor 5400 Series	1
1 Introduction	9
1.1 Terminology	10
1.2 State of Data	13
1.3 References	13
2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	16
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.4.2 PLL Power Supply	18
2.5 Voltage Identification (VID)	18
2.6 Reserved, Unused, and Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	38
2.13.3 Die Voltage Validation	39
2.14 AGTL+ FSB Specifications	39
3 Mechanical Specifications	43
3.1 Package Mechanical Drawings	43
3.2 Processor Component Keepout Zones	47
3.3 Package Loading Specifications	47
3.4 Package Handling Guidelines	48
3.5 Package Insertion Specifications	48
3.6 Processor Mass Specifications	48
3.7 Processor Materials	48
3.8 Processor Markings	48
3.9 Processor Land Coordinates	49
4 Land Listing	51
4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments	51
4.1.1 Land Listing by Land Name	51
4.1.2 Land Listing by Land Number	61
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	90
6.2 Processor Thermal Features	90
6.2.1 Intel® Thermal Monitor Features	90
6.2.2 On-Demand Mode	92
6.2.3 PROCHOT# Signal	93
6.2.4 FORCEPR# Signal	93
6.2.5 THERMTRIP# Signal	94
6.3 Platform Environment Control Interface (PECI)	94
6.3.1 Introduction	94
6.3.2 PECI Specifications	96
7 Features	97
7.1 Power-On Configuration Options	97
7.2 Clock Control and Low Power States	97
7.2.1 Normal State	98
7.2.2 HALT or Extended HALT State	98
7.2.3 Stop-Grant State	100
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	101
7.3 Enhanced Intel SpeedStep® Technology	101
8 Boxed Processor Specifications	103
8.1 Introduction	103
8.2 Mechanical Specifications	105
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	105
8.2.2 Boxed Processor Heat Sink Weight	113
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	113
8.3 Electrical Requirements	113
8.3.1 Fan Power Supply (Active CEK)	113
8.3.2 Boxed Processor Cooling Requirements	114
8.4 Boxed Processor Contents	115
9 Debug Tools Specifications	117
9.1 Debug Port System Requirements	117
9.2 Target System Implementation	117
9.2.1 System Implementation	117
9.3 Logic Analyzer Interface (LAI)	117
9.3.1 Mechanical Considerations	118

Intel E5472 Data Sheet - Page 78

Table 5-1., Signal Definitions Sheet 8 of 8

Page 78 highlights