Intel E5472 Data Sheet - Page 75

Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 8) Name GTLREF_DATA_MID GTLREF_DATA_END HIT# HITM# IERR# IGNNE# INIT# LINT[1:0] LL_ID[1:0] LOCK# Type Description Notes I GTLREF_DATA determines the signal reference level for AGTL+ data input lands. GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-19 and the appropriate platform design guidelines for additional details. I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop 3 I/O operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. O IERR# (Internal Error) is asserted by a processor as the result of an 2 internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination. I IGNNE# (Ignore Numeric Error) is asserted to force the processor to 2 ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. I INIT# (Initialization), when asserted, resets integer registers inside 2 all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor FSB agents. I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins 2 of all FSB agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous. These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. O The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. These signals are not connected to the processor die. I/O LOCK# indicates to the system that a transaction must occur 3 atomically. This signal must connect the appropriate pins of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. 75