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Intel E5472 Data Sheet - Page 102

for the Stop Clock State Machine for supported P

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Features Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points which are lower power capability states within the Normal state (see Figure 7-1 for the Stop Clock State Machine for supported Pstates). Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Quad-Core Intel® Xeon® Processor 5400 Series has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset dependency. - If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. - If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. § 102

Section	Page
Quad-Core Intel® Xeon® Processor 5400 Series	1
1 Introduction	9
1.1 Terminology	10
1.2 State of Data	13
1.3 References	13
2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	16
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.4.2 PLL Power Supply	18
2.5 Voltage Identification (VID)	18
2.6 Reserved, Unused, and Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	38
2.13.3 Die Voltage Validation	39
2.14 AGTL+ FSB Specifications	39
3 Mechanical Specifications	43
3.1 Package Mechanical Drawings	43
3.2 Processor Component Keepout Zones	47
3.3 Package Loading Specifications	47
3.4 Package Handling Guidelines	48
3.5 Package Insertion Specifications	48
3.6 Processor Mass Specifications	48
3.7 Processor Materials	48
3.8 Processor Markings	48
3.9 Processor Land Coordinates	49
4 Land Listing	51
4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments	51
4.1.1 Land Listing by Land Name	51
4.1.2 Land Listing by Land Number	61
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	90
6.2 Processor Thermal Features	90
6.2.1 Intel® Thermal Monitor Features	90
6.2.2 On-Demand Mode	92
6.2.3 PROCHOT# Signal	93
6.2.4 FORCEPR# Signal	93
6.2.5 THERMTRIP# Signal	94
6.3 Platform Environment Control Interface (PECI)	94
6.3.1 Introduction	94
6.3.2 PECI Specifications	96
7 Features	97
7.1 Power-On Configuration Options	97
7.2 Clock Control and Low Power States	97
7.2.1 Normal State	98
7.2.2 HALT or Extended HALT State	98
7.2.3 Stop-Grant State	100
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	101
7.3 Enhanced Intel SpeedStep® Technology	101
8 Boxed Processor Specifications	103
8.1 Introduction	103
8.2 Mechanical Specifications	105
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	105
8.2.2 Boxed Processor Heat Sink Weight	113
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	113
8.3 Electrical Requirements	113
8.3.1 Fan Power Supply (Active CEK)	113
8.3.2 Boxed Processor Cooling Requirements	114
8.4 Boxed Processor Contents	115
9 Debug Tools Specifications	117
9.1 Debug Port System Requirements	117
9.2 Target System Implementation	117
9.2.1 System Implementation	117
9.3 Logic Analyzer Interface (LAI)	117
9.3.1 Mechanical Considerations	118

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Features

102

Enhanced Intel SpeedStep Technology creates processor performance states (P-states)

or voltage/frequency operating points which are lower power capability states within

the Normal state (see

Figure 7-1

for the Stop Clock State Machine for supported P-

states). Enhanced Intel SpeedStep Technology enables real-time dynamic switching

between frequency and voltage points. It alters the performance of the processor by

changing the bus to core frequency ratio and voltage. This allows the processor to run

at different core frequencies and voltages to best serve the performance and power

requirements of the processor and system. The Quad-Core Intel® Xeon® Processor

5400 Series has hardware logic that coordinates the requested voltage (VID) between

the processor cores. The highest voltage that is requested for either of the processor

cores is selected for that processor package. Note that the front side bus is not altered;

only the internal core frequency is changed. In order to run at reduced power

consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep Technology:

•

Multiple voltage/frequency operating points provide optimal performance at

reduced power consumption.

•

Voltage/frequency selection is software controlled by writing to processor MSR’s

(Model Specific Registers), thus eliminating chipset dependency.

—

If the target frequency is higher than the current frequency, V

is incremented

in steps (+12.5 mV) by placing a new value on the VID signals and the

processor shifts to the new frequency. Note that the top frequency for the

processor can not be exceeded.

—

If the target frequency is lower than the current frequency, the processor shifts

to the new frequency and V

is then decremented in steps (-12.5 mV) by

changing the target VID through the VID signals.