Intel E5472 Data Sheet - Page 25

Input Device Hysteresis

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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Vin Vhysteresis Vn Vp Isource Isink Ileak+ IleakCbus Vnoise Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) High impedance state leakage to VTT (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance per node Signal noise immunity above 300 MHz Min -0.150 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 N/A N/A N/A 0.1 * VTT Max VTT N/A 0.500 * VTT 0.725 * VTT N/A Units Notes1 V V V V mA 1.0 mA 50 µA 2 10 µA 2 10 N/A pF 3 Vp-p Note: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 2.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Maximum VN Minimum VN PECI Ground PECI High Range PECI Low Range Minimum Valid Input Hysteresis Signal Range 25

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25
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Note:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
2.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 2-1
as a guide for input buffer design.
Table 2-10.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A
V
V
n
Negative-edge threshold
voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold
voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state leakage
to V
TT
(V
leak
= V
OL
)
N/A
50
μA
2
I
leak-
High impedance leakage to
GND
(V
leak
= V
OH
)
N/A
10
μA
2
C
bus
Bus capacitance per node
N/A
10
pF
3
V
noise
Signal noise immunity above
300 MHz
0.1 * V
TT
N/A
V
p-p
Figure 2-1.
Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TT
PECI Ground