Intel E5472 Data Sheet - Page 24

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications

24

2.8

CMOS Asynchronous and Open Drain

Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,

and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain

signals are required to be asserted/deasserted for at least eight BCLKs in order for the

processor to recognize the proper signal state. See

Section 2.13

for the DC

specifications. See

Chapter 6

for additional timing requirements for entering and

leaving the low power states.

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain followed by any

other components within the system. A translation buffer should be used to connect to

the rest of the chain unless one of the other components is capable of accepting an

input of the appropriate voltage. Similar considerations must be made for TCK, TDO,

TMS, and TRST#. Two copies of each signal may be required with each driving a

different voltage level.

2.10

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel

between Intel processors and chipset components to external thermal monitoring

devices. The Quad-Core Intel® Xeon® Processor 5400 Series contains Digital Thermal

Sensor (DTS) sprinkled both inside and outside the cores in a die. These sensors are

implemented as analog-to-digital converters calibrated at the factory for reasonable

accuracy to provide a digital representation of relative processor temperature. PECI

provides an interface to relay the highest DTS temperature within a die to external

devices for thermal/fan speed control. More detailed information may be found in the

Platform Environment Control Interface (PECI) Specification.

2.10.1

DC Characteristics

The PECI interface operates at a nominal voltage set by V

TT

. The set of DC electrical

specifications shown in

Table 2-10

is used with devices normally operating from a V

TT

interface supply. V

TT

nominal levels will vary between processor families. All PECI

devices will operate at the V

TT

level determined by the processor installed in the

system. For specific nominal V

TT

levels, refer to the appropriate processor EMTS.

Section	Page
Quad-Core Intel® Xeon® Processor 5400 Series	1
1 Introduction	9
1.1 Terminology	10
1.2 State of Data	13
1.3 References	13
2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	16
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.4.2 PLL Power Supply	18
2.5 Voltage Identification (VID)	18
2.6 Reserved, Unused, and Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	38
2.13.3 Die Voltage Validation	39
2.14 AGTL+ FSB Specifications	39
3 Mechanical Specifications	43
3.1 Package Mechanical Drawings	43
3.2 Processor Component Keepout Zones	47
3.3 Package Loading Specifications	47
3.4 Package Handling Guidelines	48
3.5 Package Insertion Specifications	48
3.6 Processor Mass Specifications	48
3.7 Processor Materials	48
3.8 Processor Markings	48
3.9 Processor Land Coordinates	49
4 Land Listing	51
4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments	51
4.1.1 Land Listing by Land Name	51
4.1.2 Land Listing by Land Number	61
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	90
6.2 Processor Thermal Features	90
6.2.1 Intel® Thermal Monitor Features	90
6.2.2 On-Demand Mode	92
6.2.3 PROCHOT# Signal	93
6.2.4 FORCEPR# Signal	93
6.2.5 THERMTRIP# Signal	94
6.3 Platform Environment Control Interface (PECI)	94
6.3.1 Introduction	94
6.3.2 PECI Specifications	96
7 Features	97
7.1 Power-On Configuration Options	97
7.2 Clock Control and Low Power States	97
7.2.1 Normal State	98
7.2.2 HALT or Extended HALT State	98
7.2.3 Stop-Grant State	100
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	101
7.3 Enhanced Intel SpeedStep® Technology	101
8 Boxed Processor Specifications	103
8.1 Introduction	103
8.2 Mechanical Specifications	105
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	105
8.2.2 Boxed Processor Heat Sink Weight	113
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	113
8.3 Electrical Requirements	113
8.3.1 Fan Power Supply (Active CEK)	113
8.3.2 Boxed Processor Cooling Requirements	114
8.4 Boxed Processor Contents	115
9 Debug Tools Specifications	117
9.1 Debug Port System Requirements	117
9.2 Target System Implementation	117
9.2.1 System Implementation	117
9.3 Logic Analyzer Interface (LAI)	117
9.3.1 Mechanical Considerations	118

Intel E5472 Data Sheet - Page 24

CMOS Asynchronous and Open Drain, Asynchronous Signals, Test Access Port TAP Connection, Platform

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