Intel E5472 Data Sheet - Page 16

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.2 2.3 2.3.1 2.3.2 2.3.3 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 VCC (power) and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions. Twenty two lands are specified as VTT, which provide termination for the FSB and provides power to the I/O buffers. The platform must implement a separate supply for these lands which meets the VTT specifications outlined in Table 2-12. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Quad-Core Intel® Xeon® Processor 5400 Series is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply voltage during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-12. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines. VCC Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR), and the baseboard designer must assure a low interconnect resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk decoupling must be provided on the baseboard to handle large voltage swings. The power delivery solution must insure the voltage and current specifications are met (as defined in Table 2-12). For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines. VTT Decoupling Bulk decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the expected load. To insure optimal performance, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines. Front Side Bus AGTL+ Decoupling The Quad-Core Intel® Xeon® Processor 5400 Series integrates signal termination on the die, as well as a portion of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines. 16