Apple IMAC User Manual - Page 60
Backside Cache, The PowerPC G3 microprocessor interfaces with SRAM
UPC - 067540444435
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Basics Backside Cache - 4 4 Backside Cache Backside cache is a significant architectural design change from earlier PowerPC processors. The main advantage of the backside cache architecture is the speed of the dedicated CPU-to-L2 cache interface. Using the dedicated bus allows the CPU to access the fast L2 cache storage through a highspeed bus without addressing the slower system bus or competing with other devices attached to the system bus. In comparison, a "far-side" cache running on the system bus would limit that SRAM interface to 50MHz. The PowerPC G3 microprocessor interfaces with SRAM storage via a dedicated bus running at various multiples of the core PLL CPU speed. With high speed L2 SRAM and a dedicated L2 bus, the CPU can access stored information up to the speed of the processor clock. L2 access is determined by the clock ratio setting. For example, with a 250 MHz