Dell PowerEdge R740xd2 EMC Installation and Service Manual - Page 26

Option, Description, Sub NUMA Cluster

Page 26 highlights

Option Description Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency supported by the processors. You can also select specific frequencies that the processors support, which can vary. For best performance, you should select Maximum data rate. Any reduction in the communication link frequency affects the performance of non-local memory accesses and cache coherency traffic. In addition, it can slow access to non-local I/O devices from a particular CPU. However, if power saving considerations outweigh performance, you might want to reduce the frequency of the CPU communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA node to minimize the impact to system performance. Virtualization Technology Enables or disables the virtualization technology for the processor. This option is set to Enabled by default. Adjacent Cache Line Prefetch Optimizes the system for applications that need high utilization of sequential memory access. This option is set to Enabled by default. You can disable this option for applications that need high utilization of random memory access. Hardware Prefetcher Enables or disables the hardware prefetcher. This option is set to Enabled by default. Software Prefetcher Enables or disables the software prefetcher. This option is set to Enabled by default. DCU Streamer Prefetcher Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to Enabled by default. DCU IP Prefetcher Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to Enabled by default. Sub NUMA Cluster Enables or disables the Sub NUMA Cluster. This option is set to Disabled by default. UPI Prefetch Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will spawn the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to Enabled by default. LLC Prefetch Enables or disables the LLC Prefetch on all threads. This option is set to Disabled by default. Dead Line LLC Alloc When enabled, it opportunistically fill dead lines in LLC. When disabled, it never fill dead lines in LLC. This option is set to Enabled by default. Directory AtoS AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes. This option is set to Disabled by default. Logical Processor Idling Enables you to improve the energy efficiency of a system. It uses the operating system core parking algorithm and parks some of the logical processors in the system which in turn allows the corresponding processor cores to transition into a lower power idle state. This option can only be enabled if the operating system supports it. It is set to Disabled by default. Configurable TDP Enables you to configure the TDP level. The available options are Nominal, Level 1, and Level 2. This option is set to Nominal by default. NOTE: This option is only available on certain stock keeping units (SKUs) of the processors. x2APIC Mode Number of Cores per Processor Processor Core Speed Processor Bus Speed Processor n Enables or disables the x2APIC mode. This option is set to Enabled by default. Controls the number of enabled cores in each processor. This option is set to All by default. Specifies the maximum core frequency of the processor. Displays the bus speed of the processor. The following settings are displayed for each processor installed in the system: Option Description Family-ModelStepping Specifies the family, model, and stepping of the processor as defined by Intel. 26 Pre-operating system management applications

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Option
Description
Maximum data rate indicates that the BIOS runs the communication links at the maximum frequency supported by
the processors. You can also select specific frequencies that the processors support, which can vary.
For best performance, you should select
Maximum data rate
. Any reduction in the communication link frequency
affects the performance of non-local memory accesses and cache coherency traffic. In addition, it can slow
access to non-local I/O devices from a particular CPU.
However, if power saving considerations outweigh performance, you might want to reduce the frequency of the
CPU communication links. If you do this, you should localize memory and I/O accesses to the nearest NUMA node
to minimize the impact to system performance.
Virtualization
Technology
Enables or disables the virtualization technology for the processor. This option is set to
Enabled
by default.
Adjacent Cache
Line Prefetch
Optimizes the system for applications that need high utilization of sequential memory access. This option is set to
Enabled
by default. You can disable this option for applications that need high utilization of random memory
access.
Hardware
Prefetcher
Enables or disables the hardware prefetcher. This option is set to
Enabled
by default.
Software
Prefetcher
Enables or disables the software prefetcher. This option is set to
Enabled
by default.
DCU Streamer
Prefetcher
Enables or disables the Data Cache Unit (DCU) streamer prefetcher. This option is set to
Enabled
by default.
DCU IP Prefetcher
Enables or disables the Data Cache Unit (DCU) IP prefetcher. This option is set to
Enabled
by default.
Sub NUMA Cluster
Enables or disables the Sub NUMA Cluster. This option is set to
Disabled
by default.
UPI Prefetch
Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will
spawn the speculative memory read to Integrated Memory Controller (iMC) directly. This option is set to
Enabled
by default.
LLC Prefetch
Enables or disables the LLC Prefetch on all threads. This option is set to
Disabled
by default.
Dead Line LLC
Alloc
When enabled, it opportunistically fill dead lines in LLC. When disabled, it never fill dead lines in LLC. This option is
set to
Enabled
by default.
Directory AtoS
AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes. This option
is set to
Disabled
by default.
Logical Processor
Idling
Enables you to improve the energy efficiency of a system. It uses the operating system core parking algorithm and
parks some of the logical processors in the system which in turn allows the corresponding processor cores to
transition into a lower power idle state. This option can only be enabled if the operating system supports it. It is set
to
Disabled
by default.
Configurable TDP
Enables you to configure the TDP level. The available options are
Nominal
,
Level 1
, and
Level 2
. This option is set
to
Nominal
by default.
NOTE:
This option is only available on certain stock keeping units (SKUs) of the processors.
x2APIC Mode
Enables or disables the x2APIC mode. This option is set to
Enabled
by default.
Number of Cores
per Processor
Controls the number of enabled cores in each processor. This option is set to
All
by default.
Processor Core
Speed
Specifies the maximum core frequency of the processor.
Processor Bus
Speed
Displays the bus speed of the processor.
Processor n
The following settings are displayed for each processor installed in the system:
Option
Description
Family-Model-
Stepping
Specifies the family, model, and stepping of the processor as defined by Intel.
26
Pre-operating system management applications