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Servo Control

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8.7 Servo Control 8.6.3 Read circuit After fixing the data output from the head IC to a certain level by Automatic Gain Control (AGC), the Read circuit converts the waveform digitally by Analog to Digital Converter (ADC) circuit via analog filter circuit. And then, after equalization by Finite Impulser Response filter (FIR filter), being converted to logic signal by Viterbi detection circuit, convert into NRZ data by 32/34 decoding circuit, and then the Read circuit sends the data to buffer memory. (1) AGC amplifier The AGC amplifier automatically keeps the output amplitude level constant, even if the input amplitude level changes. Even if the head output level changes with head characteristics and outer or inner head position, the AGC amplifier output level is constant. (2) Analog filter, ADC, FIR filter and Viterbi detection circuits AGC amplifier output is demodulated in MEEPRML method as a total process through analog filter circuit, ADC circuit, FIR filter circuit and Viterbi detection circuit. (3) 32/34 RLL decoding circuit The 32/34 RLL decoding circuit decodes the viterbi detection circuit output signal. This decoding circuit reverse converts (scrambles) the pseudorandom pattern (created at write) into NRZ data. The NRZ data is then fed to the upper-level circuit. 8.7 Servo Control The servomechanism is controlled using a digital servo technique by the firmware in the digital signal processor (DSP). DPS carries out VCM control. Control of the voice coil motor consists of track-following operation control and seek operation control. Track-following operation is controlled to center the data-headmounted actuator over the target cylinder for read/write operation. The seek operation moves the actuator to a different target cylinder at high speed. For stable operation, a variety of calibration is done (see Section 8.5). 8.7.1 Servo control circuit Figure 8.4 is the block diagram of the servo control circuit. The following explains each function of the servo control circuit. C141-E133-02EN 8-9

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	5
Preface	7
Important Alert Items	11
MANUAL ORGANIZATION	13
REFERENCED STANDARDS	15
CONTENTS	17
CHAPTER 1 General Description	25
1.1 Standard Features	26
1.2 Hardware Structure	29
CHAPTER 2 Specifications	33
2.1 Hardware Specifications	33
2.1.1 Model name and part number	33
2.1.2 Function specifications	34
2.1.3 Environmental specifications	36
2.1.4 Error rate	37
2.1.5 Reliability	37
CHAPTER 3 Data Format	41
3.1 Data Space	41
3.1.1 Cylinder configuration	41
3.1.2 Alternate spare area	44
3.1.3 Track format	45
3.1.4 Sector format	47
3.1.5 Format capacity	49
3.2 Logical Data Block Addressing	50
3.3 Defect Management	51
3.3.1 Defect list	51
3.3.2 Alternate block allocation	51
CHAPTER 4 Installation Requirements	57
4.1 Mounting Requirements	57
4.1.1 External dimensions	57
4.1.2 Mounting	59
4.1.3 Notes on mounting	59
4.2 Power Supply Requirements	63
4.3 Connection Requirements	65
4.3.1 Connector	65
4.3.2 Interface connector	65
CHAPTER 5 Installation	67
5.1 Notes on Handling Drives	67
5.2 Setting	69
5.2.1 Loop ID setting	69
5.2.2 Mode settings	69
5.3 Mounting Drives	70
5.3.1 Mounting procedures	70
5.4 Dismounting Drives	71
5.5 Checking Operation after Installation and Preparing the IDD for Use	72
5.5.1 Checking initial operation	72
5.5.2 Checking connection	73
5.5.3 Formatting	76
5.5.4 Setting parameters	78
5.6 Spare Disk Drive	82
CHAPTER 6 Diagnostics and Maintenance	83
6.1 Diagnostics	83
6.1.1 Self-diagnostics	83
6.1.2 Test programs	86
6.2 Maintenance Information	87
6.2.1 Precautions	87
6.2.2 Maintenance requirements	88
6.2.3 Maintenance levels	90
6.2.4 Revision numbers	91
6.2.5 Tools and test equipment	92
6.2.6 Tests	92
6.3 Operation Check	94
6.3.1 Initial seek operation check	94
6.3.2 Operation test	94
6.3.3 Diagnostic test	94
6.4 Troubleshooting Procedures	95
6.4.1 Outline of troubleshooting procedures	95
6.4.2 Troubleshooting with disk drive replacement in the field	95
6.4.3 Troubleshooting at the repair site	97
6.4.4 Troubleshooting with parts replacement in the factory	98
6.4.5 Finding possibly faulty parts	98
CHAPTER 7 Error Analysis	99
7.1 Error Analysis Information Collection	99
7.1.1 Sense data	99
7.1.2 Sense key, sense code, and subsense code	99
7.2 Sense Data Analysis	101
7.2.1 Error information indicated with sense data	101
7.2.2 Sense data (3-0C-03), (4-40-xx), (4-44-xx), and (4-C4-xx)	102
7.2.3 Sense data (1-1x-xx), (3-1x-xx) and (E-1D-00): Disk read error	102
7.2.4 Sense data (5-2x-xx), (5-3D-00), (5-90-00), (B-47-xx), (B-49-00), (B-4D-xx) and (B-4E-00): fibre channel interface erro	102
CHAPTER 8 Principle of Operation	103
8.1 Outline	103
8.2 Disk Drive Configuration	103
8.2.1 Disks	104
8.2.2 Heads	104
8.2.3 Spindle mechanism	104
8.2.4 Actuator	104
8.2.5 Air filters	104
8.3 Circuit Configuration	105
8.4 Power-On Sequence	107
8.5 Factory-Calibration	108
8.6 Read/Write Circuit	109
8.6.1 Head IC	109
8.6.2 Write circuit	109
8.6.3 Read circuit	111
8.7 Servo Control	111
8.7.1 Servo control circuit	111
8.7.2 Servo format	112
8.7.3 Servo frame format	114
8.7.4 Spindle motor control	114
8.7.5 Voice coil motor control	115
APPENDIX A Locations of Connector	117
A.1 Locations of Connector	118
APPENDIX B Connector Signal Allocation	119
B.1 Interface (FC-SCA) Connector Signal Allocation	120
APPENDIX C Model Names and Product Numbers	121
C.1 Model Names and Product Numbers	122
APPENDIX D Fibre Channel Interface Functions	123
D.1 Fibre Channel Interface Function Specifications	124
Glossary	133
Acronyms and Abbreviations	137
Index	139
READER’S COMMENT FORM	143

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8.7

Servo Control

C141-E133-02EN

8-9

8.6.3

Read circuit

After fixing the data output from the head IC to a certain level by Automatic Gain Control (AGC),

the Read circuit converts the waveform digitally by Analog to Digital Converter (ADC) circuit via

analog filter circuit.

And then, after equalization by Finite Impulser Response filter (FIR filter),

being converted to logic signal by Viterbi detection circuit, convert into NRZ data by 32/34 decoding

circuit, and then the Read circuit sends the data to buffer memory.

(1)

AGC amplifier

The AGC amplifier automatically keeps the output amplitude level constant, even if the input

amplitude level changes.

Even if the head output level changes with head characteristics and outer or

inner head position, the AGC amplifier output level is constant.

(2)

Analog filter, ADC, FIR filter and Viterbi detection circuits

AGC amplifier output is demodulated in MEEPRML method as a total process through analog filter

circuit, ADC circuit, FIR filter circuit and Viterbi detection circuit.

(3)

32/34 RLL decoding circuit

The 32/34 RLL decoding circuit decodes the viterbi detection circuit output signal.

This decoding

circuit reverse converts (scrambles) the pseudorandom pattern (created at write) into NRZ data.

The

NRZ data is then fed to the upper-level circuit.

8.7

Servo Control

The servomechanism is controlled using a digital servo technique by the firmware in the digital signal

processor (DSP).

DPS carries out VCM control.

Control of the voice coil motor consists of track-following operation

control and seek operation control.

Track-following operation is controlled to center the data-head-

mounted actuator over the target cylinder for read/write operation.

The seek operation moves the

actuator to a different target cylinder at high speed.

For stable operation, a variety of calibration is

done (see Section 8.5).

8.7.1

Servo control circuit

Figure 8.4 is the block diagram of the servo control circuit.

The following explains each function of

the servo control circuit.