Intel SC450NX Product Guide - Page 157

Interrupts The table below recommends the logical interrupt mapping of interrupt sources; it reflects a typical configuration, but these interrupts can be changed by the user. Use the information to determine how to program each interrupt. The actual interrupt map is defined using configuration registers in the PIIX4E and the I/O controller. I/O Redirection Registers in the I/O APIC are provided for each interrupt signal; the signals define hardware interrupt signal characteristics for APIC messages sent to local APIC(s).  NOTE To disable either IDE controller and reuse the interrupt: if you plan to disable either IDE controller to reuse the interrupt for that controller, you must physically unplug the IDE cable from the board connector (IDE0) if a cable is present. Simply disabling the drive by configuring the SSU option does not make the interrupt available. Table 53. Interrupt INTR NMI IRQ1 Cascade IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8_L IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 SMI_L Interrupts I/O APIC level INT0 N/A INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 Description Processor interrupt NMI from PIC to processor Keyboard interrupt Interrupt signal from second 8259 in PIIX4E Serial port A or B interrupt from SIO device (user can configure) Serial port A or B interrupt from SIO device (user can configure) Parallel port II Diskette port Parallel port RTC interrupt Signal control interrupt (SCI) used by ACPI-compliant OS Mouse interrupt Compatibility IDE interrupt from primary channel IDE devices 0 and 1 System management interrupt-general purpose indicator sourced by the PIIX4E and BMC through the PID to the processors 157