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Phases of operation, 5.5.3 Ultra DMA data in commands, is initiated.

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Interface device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred. 5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements). In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules. a) An Ultra DMA burst is defined as the period from an assertion of DMACKby the host to the subsequent negation of DMACK-. b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst. 5.5.3 Ultra DMA data in commands 5.5.3.1 Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated. 2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE. 3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert STOP. 4) The host shall negate HDMARDY-. 5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst. 6) Steps (3), (4) and (5) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep DMACK- asserted until the end of an Ultra DMA burst. 7) The host shall release DD (15:0) within tAZ after asserting DMACK-. 5-100 C141-E120-02EN

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Figures	18
Tables	19
CHAPTER 1 Device Overview	21
1.1 Features	22
1.1.1 Functions and performance	22
1.1.2 Adaptability	22
1.1.3 Interface	23
1.2 Device Specifications	24
1.2.1 Specifications summary	24
1.2.2 Model and product number	25
1.3 Power Requirements	25
1.4 Environmental Specifications	27
1.5 Acoustic Noise	28
1.6 Shock and Vibration	28
1.7 Reliability	29
1.8 Error Rate	30
1.9 Media Defects	30
1.10Load/Unload Function	30
CHAPTER 2 Device Configuration	33
2.1 Device Configuration	34
2.2 System Configuration	36
2.2.1 ATA interface	36
2.2.2 1 drive connection	36
2.2.3 2 drives connection	36
CHAPTER 3 Installation Conditions	39
3.1 Dimensions	40
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	49
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
CHAPTER 4 Theory of Device Operation	53
4.1 Outline	54
4.2 Subassemblies	54
4.2.1 Disk	54
4.2.2 Head	54
4.2.3 Spindle	55
4.2.4 Actuator	55
4.2.5 Air filter	55
4.3 Circuit Configuration	56
4.4 Power-on Sequence	59
4.5 Self-calibration	60
4.5.1 Self-calibration contents	60
4.5.2 Execution timing of self-calibration	61
4.5.3 Command processing during self-calibration	62
4.6 Read/write Circuit	62
4.6.1 Read/write preamplifier (HDIC)	62
4.6.2 Write circuit	62
4.6.3 Read circuit	65
4.6.4 Digital PLL circuit	66
4.7 Servo Control	67
4.7.1 Servo control circuit	67
4.7.2 Data-surface servo format	70
4.7.3 Servo frame format	72
4.7.4 Actuator motor control	73
4.7.5 Spindle motor control	74
CHAPTER 5 Interface	77
5.1 Physical Interface	78
5.1.1 Interface signals	78
5.1.2 Signal assignment on the connector	79
5.2 Logical Interface	82
5.2.1 I/O registers	83
5.2.2 Command block registers	84
5.2.3 Control block registers	89
5.3 Host Commands	89
5.3.1 Command code and parameters	90
5.3.2 Command descriptions	92
5.3.3 Error posting	164
5.4 Command Protocol	166
5.4.1 PIO Data transferring commands from device to host	166
5.4.2 PIO Data transferring commands from host to device	168
5.4.3 Commands without data transfer	170
5.4.4 Other commands	172
5.4.5 DMA data transfer commands	172
5.5 Ultra DMA Feature Set	175
5.5.1 Overview	175
5.5.2 Phases of operation	176
5.5.3 Ultra DMA data in commands	176
5.5.4 Ultra DMA data out commands	181
5.5.5 Ultra DMA CRC rules	185
5.5.6 Series termination required for Ultra DMA	186
5.6 Timing	187
5.6.1 PIO data transfer	187
5.6.2 Multiword data transfer	188
5.6.3 Ultra DMA data transfer	189
5.6.4 Power-on and reset	202
CHAPTER 6 Operations	203
6.1 Device Response to the Reset	204
6.1.1 Response to power-on	204
6.1.2 Response to hardware reset	205
6.1.3 Response to software reset	207
6.1.4 Response to diagnostic command	208
6.2 Power Save	209
6.2.1 Power save mode	209
6.2.2 Power commands	210
6.3 Defect Management	211
6.3.1 Spare area	211
6.3.2 Alternating defective sectors	211
6.4 Read-Ahead Cache	213
6.4.1 Data buffer configuration	214
6.4.2 Caching operation	214
6.4.3 Usage of read segment	216
6.5 Write Cache	222
Glossary	225
Acronyms and Abbreviations	229
Comment Form	231
Spine	233

Match case Limit results 1 per page

Interface

5-100

C141-E120-02EN

device compares its CRC data to the data sent from the host.

If the two values do

not match the device reports an error in the error register at the end of the

command.

If an error occurs during one or more Ultra DMA bursts for any one

command, at the end of the command, the device shall report the first error that

occurred.

5.5.2

Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data

in or data out bursts.

Each Ultra DMA burst has three mandatory phases of

operation:

the initiation phase, the data transfer phase, and the Ultra DMA burst

termination phase.

In addition, an Ultra DMA burst may be paused during the

data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for

each of these phases, 5.6 defines the specific timing requirements).

In the

following rules DMARDY- is used in cases that could apply to either

DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to

either DSTROBE or HSTROBE.

The following are general Ultra DMA rules.

An Ultra DMA burst is defined as the period from an assertion of DMACK-

by the host to the subsequent negation of DMACK-.

A recipient shall be prepared to receive at least two data words whenever it

enters or resumes an Ultra DMA burst.

5.5.3

Ultra DMA data in commands

5.5.3.1

Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise

specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):

The host shall keep DMACK- in the negated state before an Ultra DMA burst

is initiated.

The device shall assert DMARQ to initiate an Ultra DMA burst.

After

assertion of DMARQ the device shall not negate DMARQ until after the first

negation of DSTROBE.

Steps (3), (4) and (5) may occur in any order or at the same time.

The host

shall assert STOP.

The host shall negate HDMARDY-.

The host shall negate CS0-, CS1-, DA2, DA1, and DA0.

The host shall keep

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at

the end of the burst.

Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts

DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra

DMA burst.

The host shall release DD (15:0) within t

after asserting DMACK-.