Fujitsu MHN2150AT Manual/User Guide - Page 190

Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t2CYCTYP 240 160 120 90 tCYC 112 73 54 39 t2CYC 230 153 115 86 tDS 15 10 7 7 tDH 5 5 5 5 60 40 Typical sustained average two cycle time 25 16.8 Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) 57 38 Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) 5 4 Data setup time at recipient (from data valid until STROBE edge) (*2), (*5) 5 4.6 Data hold time at recipient (from STROBE edge until data may become invalid) (*2), (*5) tDVS tDVH tCS tCH tCVS tCVH t ZFS t DZFS t FS 70 48 31 20 6.7 4.8 6.2 6.2 6.2 6.2 6.2 4.8 15 10 7 7 5 5 5 5 5 5 5 5 70 48 31 20 6.7 10 6.2 6.2 6.2 6.2 6.2 10 0 0 0 0 0 35 70 48 31 20 6.7 25 230 200 170 130 120 Data valid setup time at sender (from data valid until STROBE edge) (*3) Data valid hold time at sender (from STROBE edge until data may become invalid) (*3) CRC word setup time at device (*2) CRC word hold time device (*2) CRC word valid setup time at host (from CRC valid until DMACK-negation) (*3) CRC word valid hold time at sender (from DMACK-negation until CRC may become invalid) (*3) Time from STROBE output released-to-driving until the first transition of critical timing Time from data output releasedto-driving until the first transition of critical timing 90 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) 5-114 C141-E120-02EN