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asserted DSTROBE and negated DMARQ and the host has asserted

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Interface after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. 5) The host shall assert STOP no sooner than t after negating RP HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. 6) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated. 7) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated. 8) The device shall release DD (15:0) no later than t after negating AZ DMARQ. 9) The host shall drive DD (15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5). 10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t after the device has MLI asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places the result of its CRC calculation on DD (15:0). 12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 14) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-. 15) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated DMACK-. 16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. ACK 5-104 C141-E120-02EN

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Figures	18
Tables	19
CHAPTER 1 Device Overview	21
1.1 Features	22
1.1.1 Functions and performance	22
1.1.2 Adaptability	22
1.1.3 Interface	23
1.2 Device Specifications	24
1.2.1 Specifications summary	24
1.2.2 Model and product number	25
1.3 Power Requirements	25
1.4 Environmental Specifications	27
1.5 Acoustic Noise	28
1.6 Shock and Vibration	28
1.7 Reliability	29
1.8 Error Rate	30
1.9 Media Defects	30
1.10Load/Unload Function	30
CHAPTER 2 Device Configuration	33
2.1 Device Configuration	34
2.2 System Configuration	36
2.2.1 ATA interface	36
2.2.2 1 drive connection	36
2.2.3 2 drives connection	36
CHAPTER 3 Installation Conditions	39
3.1 Dimensions	40
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	49
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
CHAPTER 4 Theory of Device Operation	53
4.1 Outline	54
4.2 Subassemblies	54
4.2.1 Disk	54
4.2.2 Head	54
4.2.3 Spindle	55
4.2.4 Actuator	55
4.2.5 Air filter	55
4.3 Circuit Configuration	56
4.4 Power-on Sequence	59
4.5 Self-calibration	60
4.5.1 Self-calibration contents	60
4.5.2 Execution timing of self-calibration	61
4.5.3 Command processing during self-calibration	62
4.6 Read/write Circuit	62
4.6.1 Read/write preamplifier (HDIC)	62
4.6.2 Write circuit	62
4.6.3 Read circuit	65
4.6.4 Digital PLL circuit	66
4.7 Servo Control	67
4.7.1 Servo control circuit	67
4.7.2 Data-surface servo format	70
4.7.3 Servo frame format	72
4.7.4 Actuator motor control	73
4.7.5 Spindle motor control	74
CHAPTER 5 Interface	77
5.1 Physical Interface	78
5.1.1 Interface signals	78
5.1.2 Signal assignment on the connector	79
5.2 Logical Interface	82
5.2.1 I/O registers	83
5.2.2 Command block registers	84
5.2.3 Control block registers	89
5.3 Host Commands	89
5.3.1 Command code and parameters	90
5.3.2 Command descriptions	92
5.3.3 Error posting	164
5.4 Command Protocol	166
5.4.1 PIO Data transferring commands from device to host	166
5.4.2 PIO Data transferring commands from host to device	168
5.4.3 Commands without data transfer	170
5.4.4 Other commands	172
5.4.5 DMA data transfer commands	172
5.5 Ultra DMA Feature Set	175
5.5.1 Overview	175
5.5.2 Phases of operation	176
5.5.3 Ultra DMA data in commands	176
5.5.4 Ultra DMA data out commands	181
5.5.5 Ultra DMA CRC rules	185
5.5.6 Series termination required for Ultra DMA	186
5.6 Timing	187
5.6.1 PIO data transfer	187
5.6.2 Multiword data transfer	188
5.6.3 Ultra DMA data transfer	189
5.6.4 Power-on and reset	202
CHAPTER 6 Operations	203
6.1 Device Response to the Reset	204
6.1.1 Response to power-on	204
6.1.2 Response to hardware reset	205
6.1.3 Response to software reset	207
6.1.4 Response to diagnostic command	208
6.2 Power Save	209
6.2.1 Power save mode	209
6.2.2 Power commands	210
6.3 Defect Management	211
6.3.1 Spare area	211
6.3.2 Alternating defective sectors	211
6.4 Read-Ahead Cache	213
6.4.1 Data buffer configuration	214
6.4.2 Caching operation	214
6.4.3 Usage of read segment	216
6.5 Write Cache	222
Glossary	225
Acronyms and Abbreviations	229
Comment Form	231
Spine	233

Match case Limit results 1 per page

Interface

5-104

C141-E120-02EN

after the device has generated a DSTROBE edge, then the host shall be

prepared to receive zero, one or two additional data words.

The

additional data words are a result of cable round trip delay and t

RFS

timing

for the device.

The host shall assert STOP no sooner than t

after negating

HDMARDY-.

The host shall not negate STOP again until after the Ultra

DMA burst is terminated.

The device shall negate DMARQ within t

after the host has asserted

STOP.

The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

If DSTROBE is negated, the device shall assert DSTROBE within t

after the host has asserted STOP.

No data shall be transferred during this

assertion.

The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA burst is

terminated.

The device shall release DD (15:0) no later than t

after negating

DMARQ.

The host shall drive DD (15:0) no sooner than t

ZAH

after the device has

negated DMARQ.

For this step, the host may first drive DD (15:0) with

the result of its CRC calculation (see 5.5.5).

10)

If the host has not placed the result of its CRC calculation on DD (15:0)

since first driving DD (15:0) during (9), the host shall place the result of

its CRC calculation on DD (15:0) (see 5.5.5).

11)

The host shall negate DMACK- no sooner than t

MLI

after the device has

asserted DSTROBE and negated DMARQ and the host has asserted

STOP and negated HDMARDY-, and no sooner than t

DVS

after the host

places the result of its CRC calculation on DD (15:0).

12)

The device shall latch the host's CRC data from DD (15:0) on the

negating edge of DMACK-.

13)

The device shall compare the CRC data received from the host with the

results of its own CRC calculation.

If a miscompare error occurs during

one or more Ultra DMA burst for any one command, at the end of the

command, the device shall report the first error that occurred (see 5.5.5).

14)

The device shall release DSTROBE within t

IORDYZ

after the host negates

DMACK-.

15)

The host shall neither negate STOP nor assert HDMARDY- until at least

ACK

after the host has negated DMACK-.

16)

The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at

least t

ACK

after negating DMACK.