Sharp GX30 Service Manual - Page 138

IC704 LR38863: DISPLAY CONTROLLER, Pin No., Terminal name, Input/Output, Description of terminal

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GX30 IC704 (LR38863): DISPLAY CONTROLLER Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13* Terminal name DUMMY4 VDDPLL PLLGND PLLDIV0 PLLDIV1 HSD0 HSD1 HSD2 HSWRD HSEN HSCK DUMMY3 PWM1/PORT8 Input/Output - - - Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output - Output 14 PLLDIV2 Input 15 VDDCORE - 16 GND - 17 SUBWR_B Input/Output 18 GND - 19 VDDCORE - 20 PWM0/PORT3 Output 21 SUBCS_B Input/Output 22 CS_B Input/Output 23 VDDIO - 24 LCDINT Output 25 GTDIO_B Output 26 VDDIO - 27 SUBDB1 Input/Output 28 BDATA[5] (B5) Output 29 BDATA[5] (B4) Output 30 BDATA[5] (B3) Output 31 GND - 32 TESTI Input 33 BSHS_B Input/Output 34 WR_B Input/Output 35 SUBRS Input/Output 36 MP4 RESET_B Output 37 HSD6 Input/Output 38 BDATA[2] (B2) Output 39 BDATA[2] (B1) Output 40 BDATA[2] (B0) Output 41* EXCS_B1 Input/Output 42* XOUT Output 43 VDDIO - 44 GND - 45 SCANEN Input 46 RD_B 47 RSP Input/Output Input/Output 48 GND 49 HSD3 50 DCLK 51 VSYNC 52 HSYNC 53* EXCS_B3 54 XIN 55 SUBDB6 56 RESET_B - Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input CONFIDENTIAL Description of terminal Dummy 4 PLL Power supply 1.8 V (1.6 V~ 2.0 V) PLL Ground PLL multiply switching signal PLL multiply switching signal Data bus for high-speed serial transfer Data bus for high-speed serial transfer Data bus for high-speed serial transfer Read/Write determination signal for high-speed serial transfer High-speed serial data effective signal High is active Standard clock for high-speed serial transfer (5 to 33 MHz) Dummy 3 PWM output 1 General-purpose PORT output (default) (Not used) PLL multiply switching signal CORE Power supply 1.8 V (1.6 V~ 2.0 V) Logic ground Light signal for External display Logic ground CORE Power supply 1.8 V (1.6 V~ 2.0 V) PWM output 0 General-purpose PORT output (default) Chip select signal for External display Device select signal (Display is active when CS_B is "Low") IO Power supply 3.0 V (2.7 V~ 3.3 V) External interrupt signal (Starting varies when interruption occurs.) MPEG4ASIC internal core power-cut signal ("Low" is active.) IO Power supply 3.0 V (2.7 V~ 3.3 V) Data bus for External display Display panel B output signa Display panel B output signa Display panel B output signa Logic ground Test terminal (Connected to GND normally) External Bit Stream horizontal synchronization signal ("Low" is active) Host write strobe signal Data determination signal for External display MPEG4ASIC reset control signal ("Low" is active) Data bus for high-speed serial transfer Display panel B output signal Display panel B output signal Display panel B output signal Chip select output 1 (internal decode output) (Not used) Oscillation circuit output (Not used) IO Power supply 3.0 V (2.7 V~ 3.3 V) Logic ground Full scan effective signal "High" is active (Connected to GND normally) Host read strobe signal Register selection signal HOST_IF section : RSP = Low...Display access RSP = High...Control access Hyper_Serial section : RSP = Low...Control acces RSP = High...Display access Logic ground Data bus for high-speed serial transfer Data sampling clock (display clock) Vertical synchronization signal Horizontal synchronization signal Chip select output 3 (internal decode output) (Not used) Oscillation circuit input/External clock input signal Clock input for full scan Data bus for External display Master reset (All registers are initialized when Low is activated) 6 - 18

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GX30
6 – 18
CONFIDENTIAL
IC704 (LR38863): DISPLAY CONTROLLER
Pin No.
Terminal name
Input/Output
Description of terminal
1
DUMMY4
–
Dummy 4
2
VDDPLL
–
PLL Power supply 1.8 V (1.6 V~ 2.0 V)
3
PLLGND
–
PLL Ground
4
PLLDIV0
Input
PLL multiply switching signal
5
PLLDIV1
Input
PLL multiply switching signal
6
HSD0
Input/Output
Data bus for high-speed serial transfer
7
HSD1
Input/Output
Data bus for high-speed serial transfer
8
HSD2
Input/Output
Data bus for high-speed serial transfer
9
HSWRD
Input/Output
Read/Write determination signal for high-speed serial transfer
10
HSEN
Input/Output
High-speed serial data effective signal High is active
11
HSCK
Input/Output
Standard clock for high-speed serial transfer (5 to 33 MHz)
12
DUMMY3
–
Dummy 3
13*
PWM1/PORT8
Output
PWM output 1
General-purpose PORT output (default) (Not used)
14
PLLDIV2
Input
PLL multiply switching signal
15
VDDCORE
–
CORE Power supply 1.8 V (1.6 V~ 2.0 V)
16
GND
–
Logic ground
17
SUBWR_B
Input/Output
Light signal for External display
18
GND
–
Logic ground
19
VDDCORE
–
CORE Power supply 1.8 V (1.6 V~ 2.0 V)
20
PWM0/PORT3
Output
PWM output 0
General-purpose PORT output (default)
21
SUBCS_B
Input/Output
Chip select signal for External display
22
CS_B
Input/Output
Device select signal (Display is active when CS_B is “Low”)
23
VDDIO
–
IO Power supply 3.0 V (2.7 V~ 3.3 V)
24
LCDINT
Output
External interrupt signal (Starting varies when interruption occurs.)
25
GTDIO_B
Output
MPEG4ASIC internal core power-cut signal (“Low” is active.)
26
VDDIO
–
IO Power supply 3.0 V (2.7 V~ 3.3 V)
27
SUBDB1
Input/Output
Data bus for External display
28
BDATA[5] (B5)
Output
Display panel B output signa
29
BDATA[5] (B4)
Output
Display panel B output signa
30
BDATA[5] (B3)
Output
Display panel B output signa
31
GND
–
Logic ground
32
TESTI
Input
Test terminal (Connected to GND normally)
33
BSHS_B
Input/Output
External Bit Stream horizontal synchronization signal (“Low” is active)
34
WR_B
Input/Output
Host write strobe signal
35
SUBRS
Input/Output
Data determination signal for External display
36
MP4 RESET_B
Output
MPEG4ASIC reset control signal (“Low” is active)
37
HSD6
Input/Output
Data bus for high-speed serial transfer
38
BDATA[2] (B2)
Output
Display panel B output signal
39
BDATA[2] (B1)
Output
Display panel B output signal
40
BDATA[2] (B0)
Output
Display panel B output signal
41*
EXCS_B1
Input/Output
Chip select output 1 (internal decode output) (Not used)
42*
XOUT
Output
Oscillation circuit output (Not used)
43
VDDIO
–
IO Power supply 3.0 V (2.7 V~ 3.3 V)
44
GND
–
Logic ground
45
SCANEN
Input
Full scan effective signal “High” is active
(Connected to GND normally)
46
RD_B
Input/Output
Host read strobe signal
47
RSP
Input/Output
Register selection signal
HOST_IF section : RSP = Low...Display access
RSP = High...Control access
Hyper_Serial section : RSP = Low...Control acces
RSP = High...Display access
48
GND
–
Logic ground
49
HSD3
Input/Output
Data bus for high-speed serial transfer
50
DCLK
Input/Output
Data sampling clock (display clock)
51
VSYNC
Input/Output
Vertical synchronization signal
52
HSYNC
Input/Output
Horizontal synchronization signal
53*
EXCS_B3
Input/Output
Chip select output 3 (internal decode output) (Not used)
54
XIN
Input
Oscillation circuit input/External clock input signal
Clock input for full scan
55
SUBDB6
Input/Output
Data bus for External display
56
RESET_B
Input
Master reset (All registers are initialized when Low is activated)