Sharp GX30 Service Manual - Page 141

CONFIDENTIAL GX30 TESTI SCANEN RESET_B PLLDIV[2:0] Reset Halt Ctrl XOUT Oscillation circuit XIN/ SCANCK SCANCK Oscillation ON/OFF Dividing PLL Some MHz to 68 MHz PLL Clock Generator MasterClock (MCLK) ·····VRAM/HOST/HS/BS/ Some MHz to 33 MHz VDIF/VSPetc LCDTimingClock (TCLK) ·····TG/Pallet/LCD IF 5MHz~10MHz SUBLCDTimingClock (STCK) XIN clock /CDE/BS ·····SUB TEST LowSpeedClock (LCLK) ·····SIO 100 kHz~200 kHz PWMClock (PCLK) ·····PWM XIN clock MPEGClock (MPCLK) ·····External MPEG4_ASIC 15.36MHz or XIN CameraClock (CAMCK) ·····External CAMERA_DSP Approx.16.128 MHz FULL Scan SEL ReadDATA (72bit) Current consumption is decreased in a standby mode. BUFOFF_B DB[15:0] RSP RD_B WR_B CS_B WAIT_B LCDINT HSWRD HSEN HSCK HSD[7:0] HOST Interface SEL MCLK system buffer Registor VideoDisplay IF VDRD ReadDATA Read Buffer 6 bit x 4 WriteDATA CPU system buffer Format conversion circuit Conversion from YUV to RGB (Available for highspeed pipelines) Pallet gamma circuit RAM for mag/dif/sol For error diffusion LINE_Buffer (160 pixels x 36 x 1) Buffer RAM for 1 line For magnification function/ 3D data sort function LINE_Buffer (160 pixels x 48 x 4) Buffer RAM for 1 line Buffer RAM for 1 line Buffer RAM for 1 line Buffer RAM for 1 line RACK RACK SEL VideoSignalProcessor Magnify Magnification circuit Diffusion Error diffusion circuit WACK WREQ 72 Bus Controller Available for magnification function Address Generator Memory Interface ·18 bit x 4 ·Vertical and horizontal access (No limitation for the start address) ·Available for mask bit Display size 320 x 240 Pixel 260,000 colors ADDRESS DECODE DCS_B DA[1:0] EXCS_B[3:0] SEL PalletRAM Pallet RAM(R) 8bitx256 RAM(G) RAM(B) Solidify 3D circuit Buffer 18bitx4 72bit BS_DATA[71:0] RAM for BS mag/sol For BS magnification function/ 3D data sort function LINE_Buffer (160 pixels x 48 x 4) Buffer RAM for 1 line Buffer RAM for 1 line Buffer RAM for 1 line Buffer RAM for 1 line BS circuit Buffer 18bitx4 SEL Magnify Solidify Magnification circuit 3D circuit MaskBit Memory 320x240 Pixcel (2bit) RW Command function (Transmission) ColorDepthExpand RED Pallet BLUE Pallet Available for 260,000 colors R[5:0] B[5:0] Palette I/F STKCHK Bit Stream circuit A Available for MPEG4 BS_CLK MCLK phase conversion Buffer control creation UV determination and latch control signal creation Buffer section BUF_ BUF_ DATA0 DATA1 32bit RGB 32bit RGBOUT0,2 Commonly used for sub-LCD VRAM Conversion from YUV to RGB PIO for External MPEG4ASIC clock control output YUVIN0,2 H/V effective signal creation UV determination and latch circuit Conversion from 8-bit to 16-bit Display Memory 6bit 320x240 Pixcel 6bit (18bitx4 =72bit) 6bit 17bit Available for sub-LCD 130,000 colors Equivalent to LR38840 I/F Timing Control 17 8bit 4SCAN FRC CPU_DataBus DB[7:0] R[4:0],B[4:0] CDE Red Palette Green Palette Blue Palette Selector LCD Panel Interface LCD Output Timing Generator 4-wire SO/PO PWM/ PO PO SE_LD2/PORT5 SE_LD3/PORT6 PWM0/PORT3 PWMLCD/PORT4 PWM1/PORT8 SE_DO/PORT0 SE_CK/PORT1 SE_LD1/PORT2 SE_DI/PORT7 DCLK HSYNC VSYNC LCD I/F RDATA[5:0] GDATA[5:0] BDATA[5:0] BSVS_B BSHS_B BSBLK_B 5~20MHzmax BSCLK BSPIXEL[7:0] MP4RESET_B GTDIO_B MP4_P0 MP4_PLLCK CAMCK SUBCKS SUBCK SUBRS SUBCS_B SUBWR_B SUBFLMIN SUBLPIN SUBDB[7:0] 6 - 21