Foxconn Destroyer English Manual. - Page 49

3 new capabilities and prompt the user to set PC boot parameters for guaranteed optimized settings. AM2+ CPU - Select [Disabled] to turn off SLI-Memory feature. Select [CPUOC 0%] to enable using SLI-Memory SPD data to run your system. If overclock is needed, you have to adjust memory or CPU clocks from other BIOS options to overclock your system manually. AM2 CPU - Select [Disabled] to turn off SLI-Memory feature. Select any [CPUOC] item will enable SLI-Memory feature. Choose [CPUOC 0%] to use SLI-Memory SPD data to run your system. In ad- dition, you can further select from [CPUOC 1%] to [CPUOC MAX] to overclock CPU and the memory speed will change accordingly. ► SPD Checksum Restart The Serial Presence Detect (SPD) device is a small EEPROM chip, mounted on a DDR mem- ory module. This item allows you to check if the memory fails when booting. Select [Ignore], the system will not check memory module. Select [Exit], system will check, report error if there is any, then stop booting. ► CKE Based Power Down Mode This item allows you to enable or disable the CKE base power down mode. ► CKE Based Power Down CKE power down mode selection. ► Memclock Tri-stating Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. ► Memory Hole Remapping This item is used to enable/disable memory remapping around memory hole. PCI doesn't actu- ally care much which addresses are used, but by convention the PC platform puts them at the top of the 32-bit address space. For many years it wasn't possible or practical to put that much RAM into a PC. But now it is, so it's up to the memory controller and host bridge to figure out what to do. Many systems cause that high RAM to simply be ignored, resulting in the loss of effective RAM. More complex systems will take the RAM that would occupy that 3.5-4GB address space and re-map it into the 4.0-4.5 address space. The RAM doesn't care because it's just an array of storage cells, it's up to the memory controller to associate addresses with those storage cells. Of course, that only works if you're using a 64-bit (or 32-bit physical ad- dress extension (PAE) enabled) OS that can deal with physical addresses larger than 32 bits. Once this option is enabled, the BIOS can see 4096MB of memory. ► Auto Optimize Bottom IO Auto optimize maximum DRAM size when kernel assigns PCI resources done. ► Bottom of [31:24] IO Space Select bottom of [31:24] IO space manually when "Auto Optimize Bottom IO" option is disa- bled. ► Bottom of UMA DRAM [31:24] This is a memory allocation method addition to the Unified Memory Architecture (UMA) con- cept. Normally, select the default value. ► DRAM Timing Selectable This item is used to enable/disable provision of DRAM timing by SPD device. The Serial Presence Detect (SPD) device is a small EEPROM chip, mounted on a DDR3 memory module. It contains important information about the module's speed, sizze, addressing mode and various other pa- 42