IBM DTTA-351010 Hard Drive Specifications - Page 33
PIO Timings
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6.2.2 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. CS0, CS1 +DA0 2 DIOR, DIOW < T1 > < < < T9 > T0 > T2 > < T2I > Write data +DD00 15 < T3 > < T4 > Read data +DD00 15 HIOCS16 > T7 < < T10 > < T5 > T6 < > T8 < +IORDY < T11 > PARAMETER DESCRIPTION T0 Cycle time T1 CS0 1, +DA00 02 valid to DIOR, DIOW active T2 DIOR, DIOW pulse width T2I DIOR, DIOW recovery T3 +DD00 15 setup to DIOW high T4 DIOW high to +DD00 15 hold T5 +DD00 15 setup to DIOR high T6 DIOR high to +DD00 15 hold T7 CS0 1, +DA00 02 valid to HIOCS16 assertion T8 CS0 1, +DA00 02 invalid to HIOCS16 negation T9 DIOR, DIOW high to CS0 1, +DA00 02 hold T10 DIOR, DIOW low to +IORDY low T11 +IORDY pulse width MIN MAX Note (nsec) (nsec) 120 25 70 25 20 10 20 5 40 1 30 1 10 35 1250 Figure 18. PIO cycle timings Notes: 1. Apply to ATA-2 (mode 0,1,2) Specification 25