IBM DTTA-351010 Hard Drive Specifications - Page 77

Device Control Register, Drive Address Register, Device/Head Register

Get IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive PDF manuals and user guides View all IBM DTTA-351010 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 77 highlights

The register contains valid data only when D R Q = 1 in the Status Register. 9.6 Device Control Register Device Control Register 7 6 5 4 3 2 1 0 1 SRST IEN 0 Figure 57. Device Control Register Bit Definitions SRST (RST) -IEN Software Reset. The device is held reset when R S T = 1 . Setting R S T = 0 re-enables the device. The host must set R S T = 1 and wait for at least 5 microseconds before setting R S T = 0 , to ensure that the device recognizes the reset. Interrupt Enable. When - I E N = 0 , and the device is selected, device interrupts to the host will be enabled. When - I E N = 1 , or the device is not selected, device interrupts to the host will be disabled. 9.7 Drive Address Register Drive Address Register 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Figure 58. Drive Address Register This register contains the inverted drive select and head select addresses of the currently selected drive. Bit Definitions HIZ High Impedance. This bit is not drived and will always be in a high impedance state. -WTG -Write Gate. This bit is 0 when writing to the disk device is in progress. -H3,-H2,-H1,-H0 -Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. -H0 is the least significant. -DS1 -Drive Select 1. Drive select bit for device 1, active low. D S 1 = 0 when device 1 (slave) is selected and active. -DS0 -Drive Select 0. Drive select bit for device 0, active low. D S 0 = 0 when device 0 (master) is selected and active. 9.8 Device/Head Register Registers 69

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
The register contains valid data only when DRQ=1 in the Status Register.
9.6
Device Control Register
Device Control Register
7
6
5
4
3
2
1
0
1
SRST
IEN
0
Figure 57. Device Control Register
Bit Definitions
SRST (RST)
Software Reset.
The device is held reset when RST=1.
Setting R S T = 0 re-enables
the device.
The
host must
set RST=1
and wait for at
least 5 microseconds
before setting
RST=0, to ensure that the device recognizes the reset.
-IEN
Interrupt Enable.
When -IEN=0, and the device is selected, device interrupts to the
host will be enabled.
When -IEN=1, or the device is not selected, device interrupts
to the host will be disabled.
9.7
Drive Address Register
Drive Address Register
7
6
5
4
3
2
1
0
HIZ
WTG
H3
H2
H1
H0
DS1
DS0
Figure 58. Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ
High Impedance.
This bit is not drived and will always be in a high impedance state.
-WTG
-Write Gate.
This bit is 0 when writing to the disk device is in progress.
-H3,-H2,-H1,-H0
-Head Select.
These four bits are the one's complement of the binary coded address
of the currently selected head. -H0 is the least significant.
-DS1
-Drive Select 1.
Drive select bit for device 1, active low.
DS1=0 when device 1
(slave) is selected and active.
-DS0
-Drive Select 0.
Drive select bit for device 0, active low.
DS0=0 when device 0
(master) is selected and active.
9.8
Device/Head Register
Registers
69