IBM DTTA-351010 Hard Drive Specifications - Page 78

Error Register

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Device/Head Register 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 Figure 59. Device/Head Register This register contains the device and head numbers. Bit Definitions L Binary encoded address mode select. When L = 0 , addressing is by CHS mode. When L = 1 , addressing is by LBA mode. DRV Device. When D R V = 0 , device 0 (master) is selected. When D R V = 1 , device 1 (slave) is selected. HS3,HS2,HS1,HS0 Head Select. These four bits indicate binary encoded address of the head. HS0 is the least significant bit. At command completion, these bits are updated to reflect the currently selected head. The head number may be from zero to the number of heads minus one. In LBA mode, HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits 24-27. 9.9 Error Register 7 6 ICRCE UNC Error Register 5 4 3 2 1 0 0 IDNF 0 ABRT TK0NF AMNF Figure 60. Error Register This register contains status from the last command executed by the device, or a diagnostic code. At the completion of any command except Execute Device Diagnostic, the contents of this register are valid always even if E R R = 0 in the Status Register. Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register contains a diagnostic code. See Figure 64 on page 74 for the definition. Bit Definitions ICRCE (CRC) Interface CRC Error. C R C = 1 indicates a CRC error has occurred on the data bus during a Ultra-DMA transfer. UNC Uncorrectable Data Error. U N C = 1 indicates an uncorrectable data error has been encountered. IDNF (IDN) ID Not Found. I D N = 1 indicates the requested sector's ID field could not be found. ABRT (ABT) Aborted Command. A B T = 1 indicates the requested command has been aborted due to a device status error or an invalid parameter in an output register. 70 OEM Specifications for DTTA-3xxxxx

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Device/Head Register
7
6
5
4
3
2
1
0
1
L
1
DRV
HS3
HS2
HS1
HS0
Figure 59. Device/Head Register
This register contains the device and head numbers.
Bit Definitions
L
Binary encoded address mode select.
When L=0, addressing is by CHS mode. When
L=1, addressing is by LBA mode.
DRV
Device.
When DRV=0,
device 0 (master) is selected.
When DRV=1,
device 1
(slave) is selected.
HS3,HS2,HS1,HS0
Head Select.
These four bits indicate binary encoded address of the head.
HS0 is the
least significant bit. At command completion, these bits are updated to reflect the cur-
rently selected head.
The head number may be from zero to the number of heads minus one.
In LBA mode, HS3 through HS0 contain bits 24-27 of the LBA. At command com-
pletion, these bits are updated to reflect the current LBA bits 24-27.
9.9
Error Register
Error Register
7
6
5
4
3
2
1
0
ICRCE
UNC
0
IDNF
0
ABRT TK0NF
AMNF
Figure 60. Error Register
This register contains status from the last command executed by the device, or a diagnostic code.
At the completion of any command except Execute Device Diagnostic, the contents of this register are valid
always even if E R R = 0 in the Status Register.
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register con-
tains a diagnostic code.
See Figure 64 on page 74 for the definition.
Bit Definitions
ICRCE (CRC)
Interface CRC Error.
CRC=1 indicates a CRC error has occurred on the data bus
during a Ultra-DMA transfer.
UNC
Uncorrectable Data Error.
UNC=1 indicates an uncorrectable data error has been
encountered.
IDNF (IDN)
ID Not Found.
IDN=1 indicates the requested sector's ID field could not be found.
ABRT (ABT)
Aborted Command.
ABT=1 indicates the requested command has been aborted
due to a device status error or an invalid parameter in an output register.
70
OEM Specifications for DTTA-3xxxxx