IBM DTTA-351010 Hard Drive Specifications - Page 76

Alternate Status Register 7 6 5 4 3 2 1 0 BSY RDY DF DSC DRQ COR IDX ERR /SERV Figure 56. Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See 9.13, "Status Register" on page 71 for the definition of the bits in this register. 9.2 Command Register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Figure 71 on page 95. All other registers required for the command must be set up before writing the Command Register. 9.3 Cylinder High Register This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23. The cylinder number may be from zero to the number of cylinders minus one. 9.4 Cylinder Low Register This register contains the low order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15. The cylinder number may be from zero to the number of cylinders minus one. 9.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command, and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only. 68 OEM Specifications for DTTA-3xxxxx