IBM DTTA-351010 Hard Drive Specifications - Page 36
Multiword DMA Timings
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6.2.3.2 Multiword DMA Timings The Multiword DMA timing meets Mode 2 of the ATA-4 description. DMARQ DMACK HIOR/ HIOW READ DATA WRITE DATA < TL > < > TI < T0 > TD > < TK > > TJ < < TE > TF < > TZ < < TG > TH < PARAMETER DESCRIPTION T0 Cycle time TD HIOR, HIOW pulse width TE HIOR data setup TF HIOR data hold TG HIOW data setup TH HIOW data hold TI DMACK to HIOR/ HIOW setup TJ HIOR/ HIOW to DMACK hold TK HIOR/ HIOW nagated pulse width TL HIOR/ HIOW to DMARQ delay TZ DMACK to tristate Figure 20. Multiword D M A cycle timings [nsec] MIN MAX Note 120 70 20 5 20 10 0 5 25 35 25 28 OEM Specifications for DTTA-3xxxxx
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6.2.3.2
Multiword DMA Timings
The Multiword DMA timing meets Mode 2 of the ATA-4 description.
< TL >
DMARQ
> TJ <
DMACK
<
T0
>
> TI <
TD
><
TK
>
HIOR/ HIOW
< TE > TF <
> TZ <
READ DATA
<
TG
> TH <
WRITE DATA
[nsec]
PARAMETER DESCRIPTION
MIN
MAX
Note
T0
Cycle time
120
TD
HIOR, HIOW pulse width
70
TE
HIOR data setup
20
TF
HIOR data hold
5
TG
HIOW data setup
20
TH
HIOW data hold
10
TI
DMACK to
HIOR/ HIOW setup
0
TJ
HIOR/ HIOW to
DMACK hold
5
TK
HIOR/ HIOW nagated pulse width
25
TL
HIOR/ HIOW to
DMARQ delay
35
TZ
DMACK to tristate
25
Figure 20. Multiword DMA cycle timings
28
OEM Specifications for DTTA-3xxxxx