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Fixed I/O Map

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Technical Reference 2.3 Fixed I/O Map Table 11. I/O Map Address (hex) Size Description 0000 - 00FF 0170 - 0177 01F0 - 01F7 256 bytes 8 bytes 8 bytes Used by the Desktop Board D101GGC. Refer to the IXP 450 data sheet for dynamic addressing information. Secondary Parallel ATA IDE channel command block Primary Parallel ATA IDE channel command block 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0374 - 0377 0377, bits 6:0 0378 - 037F 03E8 - 03EF 8 bytes 8 bytes 8 bytes 8 bytes 4 bytes 7 bits 8 bytes 8 bytes LPT3 LPT2 COM4 COM2 Secondary Parallel ATA IDE channel control block Secondary IDE channel status port LPT1 COM3 03F0 - 03F5 03F6 - 03F7 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FB00 - FB07 FB08 - FB0F 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes Diskette channel Primary Parallel ATA IDE channel control block COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI Conventional bus configuration address register Reset control register PCI Conventional bus configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only NOTE Some additional I/O addresses are not available due to IXP 450 address aliasing. The IXP 450 data sheet provides more information on address aliasing. 33

Section	Page
Intel® Desktop Board D101GGC Technical Product Specification	1
Revision History	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Contents	5
1 Product Description	9
1.1 Overview	10
1.1.1 Feature Summary	10
1.1.2 Block Diagram	11
1.1.3 Board Layout	12
1.2 Online Support	14
1.3 Processor	14
1.4 System Memory	15
1.5 ATI Radeon* Xpress 200 Chipset	16
1.5.1 RC410 Graphics Subsystem	16
1.5.2 Firmware Hub (FWH)	16
1.5.3 USB	16
1.5.4 IDE Support	17
1.5.5 Real-Time Clock, CMOS SRAM, and Battery	18
1.6 PCI Express* Connectors	18
1.7 Legacy I/O Controller	19
1.7.1 Serial Port	19
1.7.2 Parallel Port	19
1.7.3 Diskette Drive Controller	19
1.7.4 Keyboard and Mouse Interface	19
1.8 High Definition Audio Subsystem	20
1.8.1 Audio Subsystem Software	20
1.8.2 Audio Connectors	21
1.9 LAN Subsystem	22
1.9.1 LAN Subsystem Software	22
1.10 Hardware Management Subsystem	23
1.10.1 Fan Monitoring	23
1.10.2 Chassis Intrusion and Detection	23
1.11 Power Management	23
1.11.1 ACPI	24
1.11.2 Hardware Support	26
2 Technical Reference	31
2.1 Memory Map	31
2.2 DMA Channels	32
2.3 Fixed I/O Map	33
2.4 Interrupts	34
2.5 PCI Configuration Space Map	35
2.6 PCI Conventional Interrupt Routing Map	35
2.7 Connectors	36
2.7.1 Back Panel Connectors	37
2.7.2 Component-side Connectors	38
2.7.3 Front Panel USB Connectors	44
2.8 Jumper Block	45
2.9 Mechanical Considerations	46
2.9.1 Form Factor	46
2.9.2 I/O Shield	47
2.10 Electrical Considerations	48
2.10.1 DC Loading	48
2.10.2 Add-in Board Considerations	48
2.10.3 Fan Connector Current Capability	49
2.10.4 Power Supply Considerations	49
2.11 Thermal Considerations	50
2.12 Reliability	52
2.13 Environmental	53
2.14 Regulatory Compliance	54
2.14.1 Safety Regulations	54
2.14.2 European Union Declaration of Conformity Statement	54
2.14.3 Product Ecology Statements	56
2.14.4 EMC Regulations	59
2.14.5 Product Certification Markings (Board Level)	60
3 Overview of BIOS Features	61
3.1 Introduction	61
3.2 BIOS Flash Memory Organization	62
3.3 Resource Configuration	62
3.3.1 PCI Autoconfiguration	62
3.3.2 PCI IDE Support	62
3.4 System Management BIOS (SMBIOS)	63
3.5 Legacy USB Support	63
3.6 BIOS Updates	64
3.6.1 Language Support	64
3.6.2 Custom Splash Screen	64
3.7 Boot Options	65
3.7.1 CD-ROM Boot	65
3.7.2 Network Boot	65
3.7.3 Booting Without Attached Devices	65
3.7.4 Changing the Default Boot Device During POST	65
3.8 Adjusting Boot Speed	66
3.8.1 Peripheral Selection and Configuration	66
3.8.2 BIOS Boot Optimizations	66
3.9 BIOS Security Features	67
4 Error Messages and Beep Codes	69
4.1 Speaker	69
4.2 BIOS Beep Code	69
4.3 BIOS Error Messages	69

Match case Limit results 1 per page

Technical Reference

2.3 Fixed I/O Map

Table 11.

I/O Map

Address (hex)

Size

Description

0000 - 00FF

256 bytes

Used by the Desktop Board D101GGC.

Refer to the

IXP 450 data sheet for dynamic addressing information.

0170 - 0177

8 bytes

Secondary Parallel ATA IDE channel command block

01F0 - 01F7

8 bytes

Primary Parallel ATA IDE channel command block

0228 - 022F

(Note 1)

8 bytes

LPT3

0278 - 027F

(Note 1)

8 bytes

LPT2

02E8 - 02EF

(Note 1)

8 bytes

COM4

02F8 - 02FF

(Note 1)

8 bytes

COM2

0374 - 0377

4 bytes

Secondary Parallel ATA IDE channel control block

0377, bits 6:0

7 bits

Secondary IDE channel status port

0378 - 037F

8 bytes

LPT1

03E8 - 03EF

8 bytes

COM3

03F0 - 03F5

6 bytes

Diskette channel

03F6 – 03F7

1 byte

Primary Parallel ATA IDE channel control block

03F8 - 03FF

8 bytes

COM1

04D0 - 04D1

2 bytes

Edge/level triggered PIC

LPTn + 400

8 bytes

ECP port, LPTn base address + 400h

0CF8 - 0CFB

(Note 2)

4 bytes

PCI Conventional bus configuration address register

0CF9

(Note 3)

1 byte

Reset control register

0CFC - 0CFF

4 bytes

PCI Conventional bus configuration data register

FB00 – FB07

8 bytes

Primary Parallel ATA IDE bus master registers

FB08 – FB0F

8 bytes

Secondary Parallel ATA IDE bus master registers

Notes:

Default, but can be changed to another address range

Dword access only

Byte access only

NOTE

Some additional I/O addresses are not available due to IXP 450 address aliasing.

The IXP 450

data sheet provides more information on address aliasing.