Intel D101GGC Product Specification - Page 70

Port 80h POST Codes - beep codes

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Intel Desktop Board D101GGC Technical Product Specification 4.4 Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST-codes requires a PCI bus add-in card, often called a POST card. The POST card can decode the port and display the contents on a medium such as a seven-segment display. Table 42 lists the Port 80h POST codes. NOTE The POST card must be installed in PCI bus connector 1. Table 42. Port 80h POST Codes POST Code CFh C0h C1h C3h C5h 01h 03h 05h 07h 08h 0Ah 0Eh 10h 12h Description of POST Operation Test CMOS read/write functionality Early chipset initialization: - Disable shadow RAM - Disable L2 cache (socket 7 or below) - Program basic chipset registers Detect memory - Auto-detection of DRAM size, type, and ECC. - Auto-detection of L2 cache Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 and F000 shadow RAM. Expand the Xgroup codes locating in physical address 1000:0 Initial SuperIO_Early_Init switch. 1. Blank out screen 2. Clear CMOS error flag 1. Clear 8042 interface 2. Initialize 8042 self-test 1. Test special keyboard controller for Winbond 977 series Super I/O chips. 2. Enable keyboard interface. 1. Disable PS/2 mouse interface (optional). 2. Auto-detect ports for keyboard and mouse followed by a port and interface swap (optional). 3. Reset keyboard for Winbond 977 series Super I/O chips. Test F000h segment shadow to see if it is read/writable. If test fails, keep beeping the speaker. Auto-detect flash type to load appropriate flash read/write codes into the run time area in F000 for ESCD and DMI support. Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status and then check for override. continued 70

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Intel Desktop Board D101GGC Technical Product Specification
70
4.4 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h.
If
the POST fails, execution stops and the last POST code generated is left at port 80h.
This code is
useful for determining the point where an error occurred.
Displaying the POST-codes requires a PCI bus add-in card, often called a POST card.
The POST
card can decode the port and display the contents on a medium such as a seven-segment display.
Table 42 lists the Port 80h POST codes.
±
NOTE
The POST card must be installed in PCI bus connector 1.
Table 42.
Port 80h POST Codes
POST Code
Description of POST Operation
CFh
Test CMOS read/write functionality
C0h
Early chipset initialization:
- Disable shadow RAM
- Disable L2 cache (socket 7 or below)
- Program basic chipset registers
C1h
Detect memory
- Auto-detection of DRAM size, type, and ECC.
- Auto-detection of L2 cache
C3h
Expand compressed BIOS code to DRAM
C5h
Call chipset hook to copy BIOS back to E000 and F000 shadow RAM.
01h
Expand the Xgroup codes locating in physical address 1000:0
03h
Initial SuperIO_Early_Init switch.
05h
1.
Blank out screen
2.
Clear CMOS error flag
07h
1.
Clear 8042 interface
2.
Initialize 8042 self-test
08h
1.
Test special keyboard controller for Winbond 977 series Super I/O chips.
2.
Enable keyboard interface.
0Ah
1.
Disable PS/2 mouse interface (optional).
2.
Auto-detect ports for keyboard and mouse followed by a port and interface swap
(optional).
3.
Reset keyboard for Winbond 977 series Super I/O chips.
0Eh
Test F000h segment shadow to see if it is read/writable.
If test fails, keep beeping the
speaker.
10h
Auto-detect flash type to load appropriate flash read/write codes into the run time area in F000
for ESCD and DMI support.
12h
Use walking 1’s algorithm to check out interface in CMOS circuitry.
Also set real-time clock
power status and then check for override.
continued