Intel D848PMB Technical Product Specification - Page 103

Table 61., Chipset Configuration Submenu

Get Intel D848PMB PDF manuals and user guides View all Intel D848PMB manuals
Add to My Manuals
Save this manual to your list of manuals

Page 103 highlights

BIOS Setup Program Table 61. Chipset Configuration Submenu (continued) Feature CPC Override SDRAM Timing Control (Note 1) SDRAM RAS Active to Precharge (Note 4) SDRAM CAS# Latency (Note 4) SDRAM RAS# to CAS# Delay (Note 4) SDRAM RAS# Precharge (Note 4) Options • Auto (default) • Enabled • Disabled • Auto (default) • Manual - Aggressive • Manual - User Defined • 8 • 7 (default) • 6 • 5 • 2.0 • 2.5 (default) • 3.0 • 4 • 3 (default) • 2 • 4 • 3 (default) • 2 Description Controls the CPC/1n rule mode. Enabled allows the DRAM controller to attempt chip select assertions in two consecutive common clocks. Auto = Timings will be programmed according to the memory detected. Manual - Aggressive = Selects most aggressive user-defined timings. Manual - User Defined = Allows manual override of detected SDRAM settings. Corresponds to tRAS. Selects the number of clock cycles required to address a column in memory. Selects the number of clock cycles between addressing a row and addressing a column. Selects the length of time required before accessing a new row. Notes: 1. This feature is displayed only if Extended Configuration is set to User Defined. 2. This option is displayed only if the installed processor has a 533 MHz system bus. 3. This option is displayed only if the installed processor has an 800 MHz system bus. 4. This feature is displayed only if SDRAM Timing Control is set to Manual - User Defined. 103

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
BIOS Setup Program
103
Table 61.
Chipset Configuration Submenu
(continued)
Feature
Options
Description
CPC Override
•
Auto (default)
•
Enabled
•
Disabled
Controls the CPC/1n rule mode.
Enabled
allows the DRAM controller to attempt chip
select assertions in two consecutive common clocks.
SDRAM Timing Control
(Note 1)
•
Auto (default)
•
Manual
–
Aggressive
•
Manual
–
User Defined
Auto
= Timings will be programmed according to the
memory detected.
Manual
–
Aggressive
= Selects most aggressive
user-defined timings.
Manual
–
User Defined
= Allows manual override of
detected SDRAM settings.
SDRAM RAS Active to
Precharge
(Note 4)
•
8
•
7 (default)
•
6
•
5
Corresponds to tRAS.
SDRAM CAS# Latency
(Note 4)
•
2.0
•
2.5 (default)
•
3.0
Selects the number of clock cycles required to
address a column in memory.
SDRAM RAS# to CAS#
Delay
(Note 4)
•
4
•
3 (default)
•
2
Selects the number of clock cycles between
addressing a row and addressing a column.
SDRAM RAS#
Precharge
(Note 4)
•
4
•
3 (default)
•
2
Selects the length of time required before accessing
a new row.
Notes:
1.
This feature is displayed only if Extended Configuration is set to User Defined.
2.
This option is displayed only if the installed processor has a 533 MHz system bus.
3.
This option is displayed only if the installed processor has an 800 MHz system bus.
4.
This feature is displayed only if SDRAM Timing Control is set to Manual
–
User Defined.