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Fixed I/O Map

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Technical Reference 2.4 Fixed I/O Map Table 14. I/O Map Address (hex) Size Description 0000 - 00FF 256 bytes Used by the Desktop Board D848PMB. Refer to the ICH5 data sheet for dynamic addressing information. 0170 - 0177 8 bytes Secondary Parallel ATE IDE channel command block 01F0 - 01F7 8 bytes Primary Parallel ATE IDE channel command block 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 8 bytes 8 bytes 8 bytes 8 bytes LPT3 LPT2 COM4 COM2 0374 - 0377 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 4 bytes 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 4 bytes Secondary Parallel ATA IDE channel control block LPT1 Intel 82848P MCH Intel 82848P MCH COM3 Diskette channel Primary Parallel ATA IDE channel control block 03F8 - 03FF 8 bytes COM1 04D0 - 04D1 2 bytes Edge/level triggered PIC LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes ECP port, LPTn base address + 400h PCI configuration address register Reset control register PCI configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only ✏ NOTE Some additional I/O addresses are not available due to ICH5 address aliassing. The ICH5 data sheet provides more information on address aliassing. For information about Obtaining the ICH5 data sheet Refer to Section 1.2 on page 16 45

Section	Page
Intel® Desktop Board D848PMB Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Notes, Cautions, and Warnings	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 Overview	12
1.1.1 Feature Summary	12
1.1.2 Manufacturing Options	13
1.1.3 Board Layout	14
1.1.4 Block Diagram	15
1.2 Online Support	16
1.3 Operating System Support	16
1.4 Design Specifications	17
1.5 Processor	20
1.6 System Memory	21
1.7 Intel® 848P Chipset	23
1.7.1 Universal 0.8 V / 1.5 V AGP 3.0 Connector	23
1.7.2 USB	24
1.7.3 IDE Support	24
1.7.4 Real-Time Clock, CMOS SRAM, and Battery	26
1.8 I/O Controller	26
1.8.1 Serial Port	27
1.8.2 Parallel Port	27
1.8.3 Diskette Drive Controller	27
1.8.4 Keyboard and Mouse Interface	27
1.9 Audio Subsystem	28
1.9.1 Audio Subsystem Software	28
1.9.2 Audio Connectors	28
1.9.3 Realtek ALC202A-based Audio Subsystem (Optional)	29
1.9.4 Intel® Flex 6 Audio Subsystem (Optional)	29
1.10 LAN Subsystem	31
1.10.1 10/100 Mbits/sec LAN Subsystem (Optional)	31
1.10.2 Gigabit LAN Subsystem (Optional)	32
1.10.3 Alert Standard Format (ASF) Support	33
1.10.4 LAN Subsystem Software	33
1.11 Hardware Management Subsystem	33
1.11.1 Hardware Monitoring and Fan Control ASIC	33
1.11.2 Thermal Monitoring	34
1.11.3 Fan Monitoring	35
1.11.4 Chassis Intrusion and Detection	35
1.12 Power Management	35
1.12.1 ACPI	35
1.12.2 Hardware Support	38
2 Technical Reference	43
2.1 Introduction	43
2.2 Memory Map	44
2.3 DMA Channels	44
2.4 Fixed I/O Map	45
2.5 PCI Configuration Space Map	46
2.6 Interrupts	47
2.7 PCI Interrupt Routing Map	48
2.8 Connectors	50
2.8.1 Back Panel Connectors	51
2.8.2 Internal I/O Connectors	52
2.8.3 External I/O Connectors	60
2.9 Jumper Blocks	64
2.9.1 Front Panel Audio Connector/Jumper Block	64
2.9.2 BIOS Setup Configuration Jumper Block	65
2.10 Mechanical Considerations	66
2.10.1 I/O Shield	67
2.11 Electrical Considerations	68
2.11.1 DC Loading	68
2.11.2 Add-in Board Considerations	68
2.11.3 Fan Connector Current Capability	68
2.11.4 Power Supply Considerations	69
2.12 Thermal Considerations	69
2.13 Reliability	72
2.14 Environmental	72
2.15 Regulatory Compliance	73
2.15.1 Safety Regulations	73
2.15.2 EMC Regulations	73
2.15.3 European Union Declaration of Conformity Statement	74
2.15.4 Product Ecology Statements	75
2.15.5 Product Certification Markings (Board Level)	75
3 Overview of BIOS Features	77
3.1 Introduction	77
3.2 BIOS Flash Memory Organization	77
3.3 Resource Configuration	78
3.3.1 PCI Autoconfiguration	78
3.3.2 PCI IDE Support	78
3.4 System Management BIOS (SMBIOS)	79
3.5 Legacy USB Support	79
3.6 BIOS Updates	80
3.6.1 Language Support	80
3.6.2 Custom Splash Screen	81
3.7 Recovering BIOS Data	81
3.8 Boot Options	82
3.8.1 CD-ROM Boot	82
3.8.2 Network Boot	82
3.8.3 Booting Without Attached Devices	82
3.8.4 Changing the Default Boot Device During POST	82
3.9 Fast Booting Systems with Intel® Rapid BIOS Boot	83
3.9.1 Peripheral Selection and Configuration	83
3.9.2 Intel Rapid BIOS Boot	83
3.10 BIOS Security Features	84
4 BIOS Setup Program	85
4.1 Introduction	85
4.2 Maintenance Menu	86
4.3 Main Menu	87
4.3.1 Additional System Information Submenu	88
4.4 Advanced Menu	89
4.4.1 PCI Configuration Submenu	90
4.4.2 Boot Configuration Submenu	91
4.4.3 Peripheral Configuration Submenu	92
4.4.4 Drive Configuration Submenu	94
4.4.5 Floppy Configuration Submenu	98
4.4.6 Event Log Configuration Submenu	99
4.4.7 Video Configuration Submenu	100
4.4.8 USB Configuration Submenu	101
4.4.9 Chipset Configuration Submenu	102
4.4.10 Fan Control Configuration Submenu	104
4.4.11 Hardware Monitoring	105
4.5 Security Menu	106
4.6 Power Menu	107
4.6.1 ACPI Submenu	107
4.7 Boot Menu	108
4.7.1 Boot Device Priority Submenu	109
4.7.2 Hard Disk Drives Submenu	110
4.7.3 Removable Devices Submenu	110
4.7.4 ATAPI CD-ROM Drives Submenu	111
4.8 Exit Menu	111
5 Error Messages and Beep Codes	113
5.1 BIOS Error Messages	113
5.2 Port 80h POST Codes	115
5.3 Bus Initialization Checkpoints	119
5.4 Speaker	120

Match case Limit results 1 per page

Technical Reference

2.4 Fixed I/O Map

Table 14.

I/O Map

Address (hex)

Size

Description

0000 - 00FF

256 bytes

Used by the Desktop Board D848PMB.

Refer to the ICH5

data sheet for dynamic addressing information.

0170 - 0177

8 bytes

Secondary Parallel ATE IDE channel command block

01F0 - 01F7

8 bytes

Primary Parallel ATE IDE channel command block

0228 - 022F

(Note 1)

8 bytes

LPT3

0278 - 027F

(Note 1)

8 bytes

LPT2

02E8 - 02EF

(Note 1)

8 bytes

COM4

02F8 - 02FF

(Note 1)

8 bytes

COM2

0374 - 0377

4 bytes

Secondary Parallel ATA IDE channel control block

0378 - 037F

8 bytes

LPT1

03B0 - 03BB

12 bytes

Intel 82848P MCH

03C0 - 03DF

32 bytes

Intel 82848P MCH

03E8 - 03EF

8 bytes

COM3

03F0 - 03F5

6 bytes

Diskette channel

03F4 - 03F7

4 bytes

Primary Parallel ATA IDE channel control block

03F8 - 03FF

8 bytes

COM1

04D0 - 04D1

2 bytes

Edge/level triggered PIC

LPTn + 400

8 bytes

ECP port, LPTn base address + 400h

0CF8 - 0CFB

(Note 2)

4 bytes

PCI configuration address register

0CF9

(Note 3)

1 byte

Reset control register

0CFC - 0CFF

4 bytes

PCI configuration data register

FFA0 - FFA7

8 bytes

Primary Parallel ATA IDE bus master registers

FFA8 - FFAF

8 bytes

Secondary Parallel ATA IDE bus master registers

Notes:

Default, but can be changed to another address range

Dword access only

Byte access only

✏

NOTE

Some additional I/O addresses are not available due to ICH5 address aliassing.

The ICH5 data

sheet provides more information on address aliassing.

For information about

Refer to

Obtaining the ICH5 data sheet

Section 1.2 on page 16