Intel D848PMB Technical Product Specification - Page 49

Table 18., PCI Interrupt Routing Map

Page 49 highlights

Technical Reference Table 18. PCI Interrupt Routing Map PCI Interrupt Source PIRQA ICH5 USB UHCI controller 1 INTA SMBus controller ICH5 USB UHCI controller 2 AC '97 ICH5 Audio ICH5 LAN ICH5 USB UHCI controller 3 ICH5 USB UHCI controller 4 INTA ICH5 USB 2.0 EHCI controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 INTD Serial ATA PIRQB INTB INTB INTA ICH5 PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTB INTC INTA INTB INTC INTD INTC INTA INTB INTA PIRQG INTB INTA PIRQH INTD INTC INTD ✏ NOTE In PIC mode, the ICH5 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 17 for the allocation of PIRQ lines to IRQ signals in APIC mode. 49

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122

Technical Reference
49
Table 18.
PCI Interrupt Routing Map
ICH5 PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
ICH5 USB UHCI controller 1 INTA
SMBus controller
INTB
ICH5 USB UHCI controller 2
INTB
AC
97 ICH5 Audio
INTB
ICH5 LAN
INTA
ICH5 USB UHCI controller 3
INTC
ICH5 USB UHCI controller 4 INTA
ICH5 USB 2.0 EHCI controller
INTD
PCI bus connector 1
INTD
INTA
INTB
INTC
PCI bus connector 2
INTC
INTB
INTA
INTD
PCI bus connector 3
INTD
INTA
INTB
INTC
Serial ATA
INTA
NOTE
In PIC mode, the ICH5 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15).
Typically, a device that does not share a PIRQ line will have a
unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal.
Refer to Table 17 for the
allocation of PIRQ lines to IRQ signals in APIC mode.