Intel S3420GPLC Product Specification - Page 124

Appendix A: Integration and Usage Tips Intel® Server Board S3420GP TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-Volt standby is still present even though the server board is powered off.  Supports only Intel® Xeon® Processor 3400 Series with 95 W and less Thermal Design Power (TDP). Does not support previous generations of the Intel® Xeon® processor.  On the back edge of the server board are diagnostic LEDs that display a sequence of amber POST codes during the boot process. If the server board hangs during POST, the LEDs displays the last POST event run before the hang.  Supports only registered DDR3 DIMMs (RDIMMs) and unbuffered DDR3 DIMMs (UDIMMs). Does not support the mixing of RDIMMs and UDIMMs.  For the best performance, the number of DDR3 DIMMs installed should be balanced across both processor sockets and memory channels. For example, a two-DIMM configuration performs better than a one-DIMM configuration. In a two-DIMM configuration, DIMMs should be installed in DIMM sockets A1 and A2. A six-DIMM configuration (DIMM socketsA1, A2, A3, B1, B2 and B3) performs better than a threeDIMM configuration (DIMM sockets A1, A2, and A3).  The Intel® Remote Management Module 3 (Intel® RMM3) connector is not compatible with the Intel® Remote Management Module (Product Order Code - AXXRMM) or Intel® Remote Management Module 2 (Product Order Code - AXXRMM2).  Clear the CMOS with the AC power cord plugged in. Removing the AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the CMOS clear procedure is followed and AC power is re-applied. If this happens, remove the AC power cord, wait 30 seconds, and then reconnect the AC power cord. Power up the system and proceed to the BIOS Setup utility to reset the needed settings.  Normal Integrated BMC functionality is disabled with the force Integrated BMC update jumper set to the "enabled" position (pins 2-3). The server should never be run with the Integrated BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default (disabled) position (pins 1-2) when the server is running normally.  When performing a normal BIOS update procedure, the BIOS recovery jumper must be set to its default position (pins 1-2). 112 Revision 2.4 Intel order number E65697-010