Intel S3420GPLC Product Specification - Page 132

Appendix C: POST Code Diagnostic LED Decoder, Intel® Server Board S3420GP TPS, Revision 2.4, Intel

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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S3420GP TPS Table 75. Diagnostic LED POST Code Decoder Checkpoint LED Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 Description Host Processor 0x04h X X X X X O X X Early processor initialization (flat32.asm) where system BSP is selected 0x10h X X X O X X X X Power-on initialization of the host processor (Boot Strap Processor) 0x11h X X X O X X X O Host processor cache initialization (including AP) 0x12h X X X O X X O X Starting application processor initialization 0x13h X X X O X X O O SMM initialization Chipset 0x21h X X O X X X X O Initializing a chipset component Memory 0x22h X X O X X X O X Reading configuration data from memory (SPD on FBDIMM) 0x23h X X O X X X O O Detecting presence of memory 0x24h X X O X X O X X Programming timing parameters in the memory controller 0x25h X X O X X O X O Configuring memory parameters in the memory controller 0x26h X X O X X O O X Optimizing memory controller settings 0x27h X X O X X O O O Initializing memory, such as ECC init 0x28h X X O X O X X X Testing memory PCI Bus 0x50h X O X O X X X X Enumerating PCI buses 0x51h X O X O X X X O Allocating resources to PCI buses 0x52h X O X O X X O X Hot Plug PCI controller initialization 0x53h X O X O X X O O Reserved for PCI bus 0x54h X O X O X O X X Reserved for PCI bus 0x55h X O X O X O X O Reserved for PCI bus 0x56h X O X O X O O X Reserved for PCI bus 0x57h X O X O X O O O Reserved for PCI bus USB 0x58h X O X O O X X X Resetting USB bus 0x59h X O X O O X X O Reserved for USB devices ATA/ATAPI/SATA 0x5Ah X O X O O X O X Resetting SATA bus and all devices 0x5Bh X O X O O X O O Detecting the presence of ATA device 0x5Ch X O X O O O X X Enable SMART if supported by ATA device 0x5Dh X O X O O O X O Reserved for ATA SMBUS 0x5Eh X O X O O O O X Resetting SMBUS 0x5Fh X O X O O O O O Reserved for SMBUS Local Console 0x70h X O O O X X X X Resetting the video controller (VGA) 0x71h X O O O X X X O Disabling the video controller (VGA) 0x72h X O O O X X O X Enabling the video controller (VGA) Remote Console 120 Revision 2.4 Intel order number E65697-010

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Appendix C: POST Code Diagnostic LED Decoder
Intel® Server Board S3420GP TPS
Revision 2.4
Intel order number E65697-010
120
Table 75. Diagnostic LED POST Code Decoder
Checkpoint
Diagnostic LED Decoder
Description
O = On, X=Off
Upper Nibble
Lower Nibble
MSB
LSB
8h
4h
2h
1h
8h
4h
2h
1h
LED
#7
#6
#5
#4
#3
#2
#1
#0
Host Processor
0x04h
X
X
X
X
X
O
X
X
Early processor initialization (flat32.asm) where system BSP is selected
0x10h
X
X
X
O
X
X
X
X
Power-on initialization of the host processor (Boot Strap Processor)
0x11h
X
X
X
O
X
X
X
O
Host processor cache initialization (including AP)
0x12h
X
X
X
O
X
X
O
X
Starting application processor initialization
0x13h
X
X
X
O
X
X
O
O
SMM initialization
Chipset
0x21h
X
X
O
X
X
X
X
O
Initializing a chipset component
Memory
0x22h
X
X
O
X
X
X
O
X
Reading configuration data from memory (SPD on FBDIMM)
0x23h
X
X
O
X
X
X
O
O
Detecting presence of memory
0x24h
X
X
O
X
X
O
X
X
Programming timing parameters in the memory controller
0x25h
X
X
O
X
X
O
X
O
Configuring memory parameters in the memory controller
0x26h
X
X
O
X
X
O
O
X
Optimizing memory controller settings
0x27h
X
X
O
X
X
O
O
O
Initializing memory, such as ECC init
0x28h
X
X
O
X
O
X
X
X
Testing memory
PCI Bus
0x50h
X
O
X
O
X
X
X
X
Enumerating PCI buses
0x51h
X
O
X
O
X
X
X
O
Allocating resources to PCI buses
0x52h
X
O
X
O
X
X
O
X
Hot Plug PCI controller initialization
0x53h
X
O
X
O
X
X
O
O
Reserved for PCI bus
0x54h
X
O
X
O
X
O
X
X
Reserved for PCI bus
0x55h
X
O
X
O
X
O
X
O
Reserved for PCI bus
0x56h
X
O
X
O
X
O
O
X
Reserved for PCI bus
0x57h
X
O
X
O
X
O
O
O
Reserved for PCI bus
USB
0x58h
X
O
X
O
O
X
X
X
Resetting USB bus
0x59h
X
O
X
O
O
X
X
O
Reserved for USB devices
ATA/ATAPI/SATA
0x5Ah
X
O
X
O
O
X
O
X
Resetting SATA bus and all devices
0x5Bh
X
O
X
O
O
X
O
O
Detecting the presence of ATA device
0x5Ch
X
O
X
O
O
O
X
X
Enable SMART if supported by ATA device
0x5Dh
X
O
X
O
O
O
X
O
Reserved for ATA
SMBUS
0x5Eh
X
O
X
O
O
O
O
X
Resetting SMBUS
0x5Fh
X
O
X
O
O
O
O
O
Reserved for SMBUS
Local Console
0x70h
X
O
O
O
X
X
X
X
Resetting the video controller (VGA)
0x71h
X
O
O
O
X
X
X
O
Disabling the video controller (VGA)
0x72h
X
O
O
O
X
X
O
X
Enabling the video controller (VGA)
Remote Console