Intel S3420GPLC Product Specification - Page 34

Functional Architecture Intel® Server Board S3420GP TPS  Existing DDR3 DIMM population  DDR3 DIMM characteristics  Optimization techniques used by the supported processors to maximize memory bandwidth In the Independent Channel mode, all DDR3 channels operate independently. Slot-to-slot DIMM matching is not required across channels (for example, A1 and B1 do not have to match each other in terms of size, organization, and timing). DIMMs within a channel do not have to match in terms of size and organization, but they operate in the minimal common frequency. Also, Independent Channel mode can be used to support single DIMM configuration in channel A and in the Single Channel mode. You must observe the following general rules when selecting and configuring memory to obtain the best performance from the system. 1. DDR3 RDIMMs must always be populated using a fill-farthest method. 2. DDR3 UDIMMs must always be populated on DIMM A1/A2/B1/B2. 3. Intel® Xeon® Processor 3400 Series support either RDIMMs or UDIMMs. 4. Intel® Xeon® Processor L3406, Intel® CoreTM Processor i3-500 series or Intel® Pentium® Processor G6950 only support UDIMMs. 5. RDIMM and UDIMM CAN NOT be mixed. 6. The minimal memory set is {DIMMA1}. 7. DDR3 DIMMs on adjacent slots on the same channel do not need to be identical. Each socket supports a maximum of six slots. Standard Intel® server boards and systems that use the Intel® 3420 chipset support three slots per DDR3 channel, two DDR3 channels per socket, and only one socket is supported on the Intel® Server Board S3420GP. 3.2.4.4 Memory Configuration Table Table 4. Memory Configuration Table RDIMM Channel A A1 A2 A3 X X X X X X X X X X X X X X X X X Channel B B1 B2 B3 X X X X X X X 22 Revision 2.4 Intel order number E65697-010