Asus Pro WS WRX90E-SAGE SE AMD TR5 Series BIOS Manual English - Page 70

SEV-ES ASID Space Limit Control [Auto], Platform First Error Handling

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Core Watchdog Core Watchdog Timer Enable Allows you to enable or disable CPU Watchdog Timer. Configuration options: [Disabled] [Enabled] [Auto] The following item appears only when Core Watchdog Timer Enable is set to [Enabled]. Core Watchdog Timer Interval Allows you to select CPU Watchdog Timer interval. Configuration options: [Auto] [39.68us] [80.64us] [162.56us] [326.4us] [654.08us] [1.309ms] [2.620ms] [5.241ms] [10.484ms] [20.970ms] [40.64ms] [82.53ms] [166.37ms] [334.05ms] [669.41ms] [1.340s] [2.681s] [5.364s] RedirectForReturnDis This option is from a workaround for GCC/C000005 issue for XV Core on CZ A0, setting MSRC001_1029 Decode Configuration (DE_CFG) bit 14 [DecfgNoRdrctForReturns] to 1. Configuration options: [Auto] [1] [0] Platform First Error Handling Allows you to enable or disable PFEH, cloack individual banks, and mask deferred error interrupts from each bank. Configuration options: [Enabled] [Disabled] [Auto] Core Performance Boost Allows you to disable Core Performance Boost. Configuration options: [Disabled] [Auto] Global C-state Control Allows you to control IO based C-state generation and DF C-states. Configuration options: [Disabled] [Enabled] [Auto] PC6 Power Supply Idle Control. Configuration options: [Low Current Idle] [Typical Current Idle] [Auto] SEV-ES ASID Space Limit Control [Auto] Allows you to select SEV-ES ASID Space Limit operation modes. Configuration options: [Auto] [Manual] The following item appears only when SEV-ES ASID Space Limit Control is set to [Manual]. SEV-ES ASID Space Limit SEV Vms using ASIDs below the SEV-ES ASID Space Limit must enable the SEV-ES feature. ASIDs from SEV-ES ASID Space Limit to (SEV ASID Count + 1) can only be used with SEV VMs. If this field is set to (SEV ASID Count + 1), all ASIDs are forced to be SEV-ES ASIDs. Hence, the valid values for this field is 1 - (SEV ASID Count + 1). Configuration options: [1] - [520] 70 Pro WS sTR5 Series BIOS Manual

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70
Pro WS sTR5 Series BIOS Manual
Core Watchdog
Core Watchdog Timer Enable
Allows you to enable or disable CPU Watchdog Timer.
Configuration options: [Disabled] [Enabled] [Auto]
The following item appears only when
Core Watchdog Timer Enable
is set to
[Enabled]
.
Core Watchdog Timer Interval
Allows you to select CPU Watchdog Timer interval.
Configuration options: [Auto] [39.68us] [80.64us] [162.56us] [326.4us] [654.08us]
[1.309ms] [2.620ms] [5.241ms] [10.484ms] [20.970ms] [40.64ms] [82.53ms] [166.37ms]
[334.05ms] [669.41ms] [1.340s] [2.681s] [5.364s]
RedirectForReturnDis
This option is from a workaround for GCC/C000005 issue for XV Core on
CZ A0, setting MSRC001_1029 Decode Configuration (DE_CFG) bit 14
[DecfgNoRdrctForReturns] to 1.
Configuration options: [Auto] [1] [0]
Platform First Error Handling
Allows you to enable or disable PFEH, cloack individual banks, and mask deferred
error interrupts from each bank.
Configuration options: [Enabled] [Disabled] [Auto]
Core Performance Boost
Allows you to disable Core Performance Boost.
Configuration options: [Disabled] [Auto]
Global C-state Control
Allows you to control IO based C-state generation and DF C-states.
Configuration options: [Disabled] [Enabled] [Auto]
PC6
Power Supply Idle Control.
Configuration options: [Low Current Idle] [Typical Current Idle] [Auto]
SEV-ES ASID Space Limit Control [Auto]
Allows you to select SEV-ES ASID Space Limit operation modes.
Configuration options: [Auto] [Manual]
The following item appears only when
SEV-ES ASID Space Limit Control
is set to
[Manual]
.
SEV-ES ASID Space Limit
SEV Vms using ASIDs below the SEV-ES ASID Space Limit must enable the SEV-ES
feature. ASIDs from SEV-ES ASID Space Limit to (SEV ASID Count + 1) can only be
used with SEV VMs. If this field is set to (SEV ASID Count + 1), all ASIDs are forced
to be SEV-ES ASIDs. Hence, the valid values for this field is 1 - (SEV ASID Count +
1).
Configuration options: [1] - [520]