Asus Pro WS WRX90E-SAGE SE AMD TR5 Series BIOS Manual English - Page 92

CXL Common Options, Infinity Fabric Frequency and Dividers

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3D V-Cache Override of X3D technology. Configuration options: [Auto] [Disable] [1 stack] [2 stack] [4 stack] Infinity Fabric Frequency and Dividers Configuration options: [Auto] [100 MHz] - [3000 MHz] PCIe Speed PWM Control Reduce link speed when devices are idle. Configuration options: [Auto] [Dynamic link speed determined by Power Management functionality] [Static Target Link Speed (GEN4)] [Static Target Link Speed (GEN5)] CXL Common Options For an AVL of components that support CXL, please contact your sales representative. CXL Control Allows you to enable or disable CXL Control on all ports. Configuration options: [Auto] [Enabled] [Disabled] CXL Encryption Configuration options: [Disabled] [Enabled] CXL SPM Set CXL memory as Special Purpose Memory. Configuration options: [Disabled] [Enabled] [Auto] CXL DVSEC Lock Lock the CXL DVSEC. Configuration options: [Disabled] [Enabled] [Auto] Temp Gen5 Advertisement Temp Gen5 Advertisementfor Alternate Protocol. Configuration options: [Disabled] [Enabled] [Auto] Sync Header Bypass Configuration options: [Disabled] [Enabled] [Auto] Speculative Reads to CXL Configuration options: [Disabled] [Enabled] [Auto] CXL RAS CXL Protocol Error Reporting Allows you to configure CXL Protocol Error reporting mechanism. Configuration options: [Disabled] [SameAsPcieAer] [ForceAerFwFirstIfCxlPresent] CXL Component Error Reporting Allows you to configure CXL Component Error reporting mechanism. Configuration options: [OS First] [FW-First] Error Isolation CXL.mem Configuration options: [Disabled] [Enabled] [Auto] 92 Pro WS sTR5 Series BIOS Manual

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92
Pro WS sTR5 Series BIOS Manual
3D V-Cache
Override of X3D technology.
Configuration options: [Auto] [Disable] [1 stack] [2 stack] [4 stack]
Infinity Fabric Frequency and Dividers
Configuration options: [Auto] [100 MHz] - [3000 MHz]
PCIe Speed PWM Control
Reduce link speed when devices are idle.
Configuration options: [Auto] [Dynamic link speed determined by Power Management
functionality] [Static Target Link Speed (GEN4)] [Static Target Link Speed (GEN5)]
CXL Common Options
For an AVL of components that support CXL, please contact your sales representative.
CXL Control
Allows you to enable or disable CXL Control on all ports.
Configuration options: [Auto] [Enabled] [Disabled]
CXL Encryption
Configuration options: [Disabled] [Enabled]
CXL SPM
Set CXL memory as Special Purpose Memory.
Configuration options: [Disabled] [Enabled] [Auto]
CXL DVSEC Lock
Lock the CXL DVSEC.
Configuration options: [Disabled] [Enabled] [Auto]
Temp Gen5 Advertisement
Temp Gen5 Advertisementfor Alternate Protocol.
Configuration options: [Disabled] [Enabled] [Auto]
Sync Header Bypass
Configuration options: [Disabled] [Enabled] [Auto]
Speculative Reads to CXL
Configuration options: [Disabled] [Enabled] [Auto]
CXL RAS
CXL Protocol Error Reporting
Allows you to configure CXL Protocol Error reporting mechanism.
Configuration options: [Disabled] [SameAsPcieAer]
[ForceAerFwFirstIfCxlPresent]
CXL Component Error Reporting
Allows you to configure CXL Component Error reporting mechanism.
Configuration options: [OS First] [FW-First]
Error Isolation CXL.mem
Configuration options: [Disabled] [Enabled] [Auto]