Gateway E-9525R Gateway E-9525R Server User Guide - Page 83

POST code checkpoints, Check, point, Description

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www.gateway.com In determining the code, Off = 0 and On = 1. Based on this, you can determine the corresponding hex code. Then, by checking "POST code checkpoints" on page 77, "Bootblock initialization code checkpoints" on page 79, "Bootblock recovery code checkpoints" on page 80, "DIM code checkpoints" on page 81, and "ACPI runtime checkpoints" on page 81, you can find out where an error is taking place. For example, if a hex code of 0B is indicated, you can detemine that the server cannot detect the PS/2 mouse. You can then take measures, such as reinserting the mouse, to solve the problem. All LEDs are cleared and restored to normal status after the server is power cycled. POST code checkpoints The following table shows the checkpoints, LED codes, and task description of events that may occur during the POST portion of the BIOS: Check Description point 03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." 04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initialize data variables that are based on CMOS setup questions. Initialize both the 8259 compatible PICs in the system. 05 Initialize the interrupt controller in hardware (generally PIC) and interrupt vector table. 06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Trap INT1Ch vector to "POSTINT1ChHandlerBlock." 08 Initialize the CPU. The BAT test is being done on KBC. The keyboard controller command byte is being programmed after Auto detection of KB/MS using AMI KB-5. C0 Early CPU Init Start - Disable Cache - Init Local APIC C1 Set up boot strap processor information. C2 Set up boot strap processor for POST. C5 Enumerate and set up application processors. C6 Re-enable cache for boot strap processor. C7 Early CPU Init Exit. 0A Initialize the 8042 compatible keyboard controller. 0B Detect the presence of PS/2 mouse. 0C Detect the presence of keyboard in KBC port. 0E Testing and initialization of different input devices. Also, update the Kernel Variables. Trap the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules. 13 Early POST initialization of chipset registers. 24 Uncompress and initialize any platform specific BIOS modules. 30 Initialize System Management Interrupt. 77

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www.gateway.com
77
In determining the code, Off = 0 and On = 1. Based on this, you can determine the corresponding
hex code. Then, by checking “POST code checkpoints” on page 77, “Bootblock initialization code
checkpoints” on page 79, “Bootblock recovery code checkpoints” on page 80, “DIM code
checkpoints” on page 81, and “ACPI runtime checkpoints” on page 81, you can find out where an
error is taking place.
For example, if a hex code of 0B is indicated, you can detemine that the server cannot detect the
PS/2 mouse. You can then take measures, such as reinserting the mouse, to solve the problem.
All LEDs are cleared and restored to normal status after the server is power cycled.
POST code checkpoints
The following table shows the checkpoints, LED codes, and task description of events that may
occur during the POST portion of the BIOS:
Check
point
Description
03
Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime
data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS
as mentioned in the Kernel Variable “wCMOSFlags.”
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum
is OK. Verify CMOS checksum manually by reading storage area. If the CMOS
checksum is bad, update CMOS with power-on default values and clear passwords.
Initialize status register A.
Initialize data variables that are based on CMOS setup questions. Initialize both the
8259 compatible PICs in the system.
05
Initialize the interrupt controller in hardware (generally PIC) and interrupt vector
table.
06
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt.
Trap INT1Ch vector to “POSTINT1ChHandlerBlock.”
08
Initialize the CPU. The BAT test is being done on KBC. The keyboard controller
command byte is being programmed after Auto detection of KB/MS using AMI KB-5.
C0
Early CPU Init Start — Disable Cache - Init Local APIC
C1
Set up boot strap processor information.
C2
Set up boot strap processor for POST.
C5
Enumerate and set up application processors.
C6
Re-enable cache for boot strap processor.
C7
Early CPU Init Exit.
0A
Initialize the 8042 compatible keyboard controller.
0B
Detect the presence of PS/2 mouse.
0C
Detect the presence of keyboard in KBC port.
0E
Testing and initialization of different input devices. Also, update the Kernel Variables.
Trap the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
Uncompress all available language, BIOS logo, and Silent logo modules.
13
Early POST initialization of chipset registers.
24
Uncompress and initialize any platform specific BIOS modules.
30
Initialize System Management Interrupt.