Intel S875WP1 Product Guide - Page 105
I/O Map, Table 46. - e pics
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I/O Map Table 46. I/O Map Address (hex) Size Description 0000 - 00FF 0170 - 0177 01F0 - 01F7 256 bytes 8 bytes 8 bytes Used by the Server Board S875WP1-E. Refer to the ICH5-R data sheet for dynamic addressing information. Secondary IDE channel Primary IDE channel 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0376 0377, bits 6:0 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F6 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 8 bytes 8 bytes 8 bytes 1 byte 7 bits 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes LPT3 LPT2 COM4/video (8514A) COM2 Secondary IDE channel command port Secondary IDE channel status port LPT1 Intel 82875P MCH Intel 82875P MCH COM3 Diskette channel 1 Primary IDE channel command port COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI configuration address register Reset control register PCI configuration data register Primary bus master IDE registers Secondary bus master IDE registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only Technical Reference 105