Intel S875WP1 Product Guide - Page 84

Table 29., Chipset Configuration Submenu, Intel Server Board S875WP1-E Product Guide - e user manual

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Table 29. Chipset Configuration Submenu (continued) Extended Configuration • Default (default) • User Defined SDRAM Frequency • Auto (default) • 266 • 333 • 400 This option is available only if User Defined is selected as the Extended Configuration option. It allows the user to override the detected memory frequency value. SDRAM Timing Control • Auto (default) • Manual - Aggressive • Manual - User Defined This option is available only if User Defined is selected as the Extended Configuration option. Auto: Timings are programmed according to the memory detected. Manual - Aggressive: Selects the most aggressive user-defined timings. Manual - User Defined: Allows manual override of detected SDRAM settings. CPC Override • Auto (default) • Enable • Disable Command Per Clock. When enabled, it allows the DRAM controller to attempt chip select assertions in two consecutive common clocks. SDRAM RAS Act. To Pre. No options SDRAM CAS# Latency No options SDRAM RAS# to CAS delay No options SDRAM RAS# Precharge No options 84 Intel Server Board S875WP1-E Product Guide

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84
Intel Server Board S875WP1-E Product Guide
Table 29.
Chipset Configuration Submenu
(continued)
Extended Configuration
•
Default (default)
•
User Defined
SDRAM Frequency
•
Auto (default)
•
266
•
333
•
400
This option is available only if User Defined is
selected as the Extended Configuration option.
It
allows the user to override the detected memory
frequency value.
SDRAM Timing Control
•
Auto (default)
•
Manual –
Aggressive
•
Manual – User
Defined
This option is available only if User Defined is
selected as the Extended Configuration option.
Auto:
Timings are programmed according to the
memory detected.
Manual – Aggressive: Selects the most aggressive
user-defined timings.
Manual – User Defined: Allows manual override of
detected SDRAM settings.
CPC Override
•
Auto (default)
•
Enable
•
Disable
Command Per Clock.
When enabled, it allows the
DRAM controller to attempt chip select assertions in
two consecutive common clocks.
SDRAM RAS Act. To Pre.
No options
SDRAM CAS# Latency
No options
SDRAM RAS# to CAS delay
No options
SDRAM RAS# Precharge
No options