Intel SE7505VB2 Product Specification - Page 99

Voltage Recovery Timing Specifications, Intel® Server Board SE7505VB2, Power Information

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Intel® Server Board SE7505VB2 Power Information 12.2.2 Voltage Recovery Timing Specifications The power supply must conform to the following specifications for voltage recovery timing under load changes: Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, 5 V and -12 V output, during instantaneous changes in load shown in the following table. Voltage regulation limits shall be maintained over the entire AC input range and any steady state temperature and operating conditions specified. Voltages shall be stable as determined by bode plot and transient response. The combined error of peak overshoot, set point, regulation, and undershoot voltage shall be less than or equal to +/-5% of the output voltage setting. The transient response measurements shall be made with a load changing repetition rate of 50 Hz to 5 kHz. The load slew rate shall not be greater than 0.2 A /µs. Output +3.3 V +5 V +12 V +5 VSB -12 V Step Load Size 4.8 A 3.0 A 10.4 A 500 mA 325 mA Table 74. Transient Load Requirements Starting Level Finishing Level 30Min. Load 30Min. Load Min. Load Min. Load Min. Load Min. load + 4.8 A and step up to max. load Min. load + 3.0 A and step up to max. load Min. load + 10.4 A and step up to max. load Min. load + 500 mA and step up to max. load Min load +325 mA and step up to max. load Slew Rate 0.50 A/µs 0.50 A/µs 0.50 A/µs 0.50 A/µs 0.50 A/µs Revision 1.2 99 Intel part number C32194-002

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Intel® Server Board SE7505VB2
Power Information
12.2.2
Voltage Recovery Timing Specifications
The power supply must conform to the following specifications for voltage recovery timing under
load changes:
±
Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, -
5 V and -12 V output, during instantaneous changes in load shown in the following table.
±
Voltage regulation limits shall be maintained over the entire AC input range and any
steady state temperature and operating conditions specified.
±
Voltages shall be stable as determined by bode plot and transient response. The
combined error of peak overshoot, set point, regulation, and undershoot voltage shall be
less than or equal to +/-5% of the output voltage setting. The transient response
measurements shall be made with a load changing repetition rate of 50 Hz to 5 kHz. The
load slew rate shall not be greater than 0.2 A /
µ
s.
Table 74. Transient Load Requirements
Output
Step Load
Size
Starting Level
Finishing Level
Slew Rate
+3.3 V
4.8 A
30Min. Load
Min. load + 4.8 A and step up to max. load
0.50 A/
µ
s
+5 V
3.0 A
30Min. Load
Min. load + 3.0 A and step up to max. load
0.50 A/
µ
s
10.4 A
Min. Load
Min. load + 10.4
A and step up to max. load
0.50 A/
µ
s
+5 VSB
500 mA
Min. Load
Min. load + 500 mA and step up to max. load
0.50 A/
µ
s
-12 V
325 mA
Min. Load
Min load +325 mA and step up to max. load
0.50 A/
µ
s
+12 V
Revision 1.2
Intel part number C32194-002
99