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Fujitsu MHT2030AT Manual/User Guide - Page 120

Ultra DMA transfer mode X

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Interface Multiword DMA transfer mode X Ultra DMA transfer mode X 00100 000 (X'20': Mode 0) 00100 001 (X'21': Mode 1) 00100 010 (X'22': Mode 2) 01000 000 (X'40': Mode 0) 01000 001 (X'41': Mode 1) 01000 010 (X'42': Mode 2) 01000 011 (X'43': Mode 3) 01000 100 (X'44': Mode 4) 01000 101 (X'45': Mode 5) *2) Advanced Power Management (APM) The host writes the Sector Count register with the desired power management level and executes this command with the Features register X'05', and then Advanced Power Management is enabled. The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any commands for a specific time. The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby. The Mode-2 level requires the longest shifting time, depending on the APM level settings. The settings of the APM level revert to their default values (Mode-1) when power-on or a hardware reset occurs for the drive. APM Level Mode 0 Active Idle → Low Power Idle Mode 1 Active Idle → Low Power Idle Mode 2 Active Idle → Low Power Idle → Standby Reserve (State Keep) Sector Count Register C0h-FEh 80h-BFh 01h-7Fh 00h, FFh Active Idle: The spindle motor rotates, and the head is loaded on the most inner position on media. Low Power Idle: The spindle motor rotates, and the head is unloaded. Standby: The spindle motor stops, and the head is unloaded. 5-46 C141-E192-02EN

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	18
Figures	18
Tables	20
CHAPTER 1 Device Overview	21
1.1 Features	22
1.1.1 Functions and performance	22
1.1.2 Adaptability	22
1.1.3 Interface	23
1.2 Device Specifications	24
1.2.1 Specifications summary	24
1.2.2 Model and product number	25
1.3 Power Requirements	26
1.4 Environmental Specifications	28
1.5 Acoustic Noise	29
1.6 Shock and Vibration	29
1.7 Reliability	30
1.8 Error Rate	31
1.9 Media Defects	31
1.10 Load/Unload Function	31
1.11 Advanced Power Management	32
CHAPTER 2 Device Configuration	35
2.1 Device Configuration	36
2.2 System Configuration	37
2.2.1 ATA interface	37
2.2.2 1 drive connection	37
2.2.3 2 drives connection	38
CHAPTER 3 Installation Conditions	39
3.1 Dimensions	40
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	49
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
3.4.5 Power Up in Standby setting	52
CHAPTER 4 Theory of Device Operation	53
4.1 Outline	54
4.2 Subassemblies	54
4.2.1 Disk	54
4.2.2 Spindle	54
4.2.3 Actuator	54
4.2.4 Air filter	55
4.3 Circuit Configuration	55
4.4 Power-on Sequence	58
4.5 Self-calibration	59
4.5.1 Self-calibration contents	59
4.5.2 Execution timing of self-calibration	60
4.5.3 Command processing during self-calibration	61
4.6 Read/write Circuit	61
4.6.1 Read/write preamplifier (PreAMP)	61
4.6.2 Write circuit	61
4.6.3 Read circuit	63
4.6.4 Digital PLL circuit	64
4.7 Servo Control	65
4.7.1 Servo control circuit	65
4.7.2 Data-surface servo format	68
4.7.3 Servo frame format	70
4.7.4 Actuator motor control	71
4.7.5 Spindle motor control	72
CHAPTER 5 Interface	75
5.1 Physical Interface	76
5.1.1 Interface signals	76
5.1.2 Signal assignment on the connector	77
5.2 Logical Interface	80
5.2.1 I/O registers	81
5.2.2 Command block registers	82
5.2.3 Control block registers	87
5.3 Host Commands	88
5.3.1 Command code and parameters	88
5.3.2 Command descriptions	92
5.3.3 Error posting	182
5.4 Command Protocol	184
5.4.1 PIO Data transferring commands from device to host	184
5.4.2 PIO Data transferring commands from host to device	187
5.4.3 Commands without data transfer	188
5.4.4 Other commands	190
5.4.5 DMA data transfer commands	190
5.5 Ultra DMA Feature Set	192
5.5.1 Overview	192
5.5.2 Phases of operation	193
5.5.3 Ultra DMA data in commands	193
5.5.4 Ultra DMA data out commands	198
5.5.5 Ultra DMA CRC rules	202
5.5.6 Series termination required for Ultra DMA	203
5.6 Timing	204
5.6.1 PIO data transfer	204
5.6.2 Multiword data transfer	205
5.6.3 Ultra DMA data transfer	206
5.6.4 Power-on and reset	219
CHAPTER 6 Operations	221
6.1 Device Response to the Reset	222
6.1.1 Response to power-on	222
6.1.2 Response to hardware reset	223
6.1.3 Response to software reset	225
6.1.4 Response to diagnostic command	226
6.2 Power Save	227
6.2.1 Power save mode	227
6.2.2 Power commands	229
6.3 Defect Processing	229
6.3.1 Spare area	229
6.3.2 Alternating processing for defective sectors	230
6.4 Read-ahead Cache	232
6.4.1 DATA buffer structure	232
6.4.2 Caching operation	233
6.4.3 Using the read segment buffer	235
6.5 Write Cache	239
6.5.1 Cache operation	239
Glossary	243
Acronyms and Abbreviations	247
Index	249
Comment Form	251