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Fujitsu MHT2030AT Manual/User Guide - Page 78

Interface

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Interface [signal] ENCSEL MSTRPUSRESETDATA 0-15 DIOWSTOP DIORHDMARDY- HSTROBE INTRQ [I/O] I I I I I/O I I I I I O [Description] This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting Pin A, B Short: Slave setting When pin C is grounded, the drive does not spin up at power on. Reset signal from the host. This signal is low active and is asserted for a minimum of 25 µs during power on. Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer Signal asserted by the host to write to the device register or data port. DIOW- must be negated by the host before starting the Ultra DMA transfer. The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer. During data transfer in Ultra DMA mode, the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended. Read strobe signal from the host to read the device register or data port Flow control signal for Ultra DMA data In transfer (READ DMA command). This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer. The host can negate the HDMARDY- signal to suspend the Ultra DMA data In transfer. Data Out Strobe signal from the host during Ultra DMA data Out transfer (WRITE DMA command). Both the rising and falling edges of the HSTROBE signal latch data from Data 15-0 into the device. The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfer. Interrupt signal to the host. This signal is negated in the following cases: − assertion of RESET- signal − Reset by SRST of the Device Control register − Write to the command register by the host − Read of the status register by the host − Completion of sector data transfer (without reading the Status register) The signal output line has a high impedance when no devices are selected or interruption is disabled. 5-4 C141-E192-02EN

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	18
Figures	18
Tables	20
CHAPTER 1 Device Overview	21
1.1 Features	22
1.1.1 Functions and performance	22
1.1.2 Adaptability	22
1.1.3 Interface	23
1.2 Device Specifications	24
1.2.1 Specifications summary	24
1.2.2 Model and product number	25
1.3 Power Requirements	26
1.4 Environmental Specifications	28
1.5 Acoustic Noise	29
1.6 Shock and Vibration	29
1.7 Reliability	30
1.8 Error Rate	31
1.9 Media Defects	31
1.10 Load/Unload Function	31
1.11 Advanced Power Management	32
CHAPTER 2 Device Configuration	35
2.1 Device Configuration	36
2.2 System Configuration	37
2.2.1 ATA interface	37
2.2.2 1 drive connection	37
2.2.3 2 drives connection	38
CHAPTER 3 Installation Conditions	39
3.1 Dimensions	40
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	49
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
3.4.5 Power Up in Standby setting	52
CHAPTER 4 Theory of Device Operation	53
4.1 Outline	54
4.2 Subassemblies	54
4.2.1 Disk	54
4.2.2 Spindle	54
4.2.3 Actuator	54
4.2.4 Air filter	55
4.3 Circuit Configuration	55
4.4 Power-on Sequence	58
4.5 Self-calibration	59
4.5.1 Self-calibration contents	59
4.5.2 Execution timing of self-calibration	60
4.5.3 Command processing during self-calibration	61
4.6 Read/write Circuit	61
4.6.1 Read/write preamplifier (PreAMP)	61
4.6.2 Write circuit	61
4.6.3 Read circuit	63
4.6.4 Digital PLL circuit	64
4.7 Servo Control	65
4.7.1 Servo control circuit	65
4.7.2 Data-surface servo format	68
4.7.3 Servo frame format	70
4.7.4 Actuator motor control	71
4.7.5 Spindle motor control	72
CHAPTER 5 Interface	75
5.1 Physical Interface	76
5.1.1 Interface signals	76
5.1.2 Signal assignment on the connector	77
5.2 Logical Interface	80
5.2.1 I/O registers	81
5.2.2 Command block registers	82
5.2.3 Control block registers	87
5.3 Host Commands	88
5.3.1 Command code and parameters	88
5.3.2 Command descriptions	92
5.3.3 Error posting	182
5.4 Command Protocol	184
5.4.1 PIO Data transferring commands from device to host	184
5.4.2 PIO Data transferring commands from host to device	187
5.4.3 Commands without data transfer	188
5.4.4 Other commands	190
5.4.5 DMA data transfer commands	190
5.5 Ultra DMA Feature Set	192
5.5.1 Overview	192
5.5.2 Phases of operation	193
5.5.3 Ultra DMA data in commands	193
5.5.4 Ultra DMA data out commands	198
5.5.5 Ultra DMA CRC rules	202
5.5.6 Series termination required for Ultra DMA	203
5.6 Timing	204
5.6.1 PIO data transfer	204
5.6.2 Multiword data transfer	205
5.6.3 Ultra DMA data transfer	206
5.6.4 Power-on and reset	219
CHAPTER 6 Operations	221
6.1 Device Response to the Reset	222
6.1.1 Response to power-on	222
6.1.2 Response to hardware reset	223
6.1.3 Response to software reset	225
6.1.4 Response to diagnostic command	226
6.2 Power Save	227
6.2.1 Power save mode	227
6.2.2 Power commands	229
6.3 Defect Processing	229
6.3.1 Spare area	229
6.3.2 Alternating processing for defective sectors	230
6.4 Read-ahead Cache	232
6.4.1 DATA buffer structure	232
6.4.2 Caching operation	233
6.4.3 Using the read segment buffer	235
6.5 Write Cache	239
6.5.1 Cache operation	239
Glossary	243
Acronyms and Abbreviations	247
Index	249
Comment Form	251

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Interface

5-4

C141-E192-02EN

[signal]

[I/O]

[Description]

ENCSEL

This signal is used to set master/slave using the CSEL signal (pin 28).

Pins B and D

Open: Sets master/slave using the CSEL signal is

disabled.

Short: Sets master/slave using the CSEL signal is

enabled.

MSTR-

MSTR, I, Master/slave setting

Pin A, B, C, D open: Master setting

Pin A, B Short:

Slave setting

PUS-

When pin C is grounded, the drive does not spin up at power on.

RESET-

Reset signal from the host.

This signal is low active and is asserted

for a minimum of 25

s during power on.

DATA 0-15

I/O

Sixteen-bit bi-directional data bus between the host and the device.

These signals are used for data transfer

DIOW-

Signal asserted by the host to write to the device register or data port.

STOP

DIOW- must be negated by the host before starting the Ultra DMA

transfer.

The STOP signal must be negated by the host before data is

transferred during the Ultra DMA transfer.

During data transfer in

Ultra DMA mode, the assertion of the STOP signal asserted by the

host later indicates that the transfer has been suspended.

DIOR-

Read strobe signal from the host to read the device register or data

port

HDMARDY-

Flow control signal for Ultra DMA data In transfer (READ DMA

command).

This signal is asserted by the host to inform the device

that the host is ready to receive the Ultra DMA data In transfer.

The

host can negate the HDMARDY- signal to suspend the Ultra DMA

data In transfer.

HSTROBE

Data Out Strobe signal from the host during Ultra DMA data Out

transfer (WRITE DMA command).

Both the rising and falling edges

of the HSTROBE signal latch data from Data 15-0 into the device.

The host can suspend the inversion of the HSTROBE signal to

suspend the Ultra DMA data Out transfer.

INTRQ

Interrupt signal to the host.

This signal is negated in the following cases:

−

assertion of RESET- signal

−

Reset by SRST of the Device Control register

−

Write to the command register by the host

−

Read of the status register by the host

−

Completion of sector data transfer

(without reading the Status register)

The signal output line has a high impedance when no devices are

selected or interruption is disabled.