Hitachi HTS541680J9AT00 Specifications - Page 144

Travelstar 5K160 (PATA) Hard Disk Drive Specification 14.34 Set Features (EFh) Command Block Output Registers Register 76543210 Data -------- Feature VVVVVVVV Sector Count Note.1, 4 LBA Low -------- LBA Mid -------- LBA High -------- Device - - -D- - - - Command 11101111 Command Block Input Registers Register 76543210 Data -------- Error ...See Below... Sector Count -------- LBA Low -------- LBA Mid -------- LBA High -------- Device -------- Status ...See Below... Error Register 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AM N 000 0 0V0 0 Figure 98 Set Features Command (EFh) Status Register 7 6543 2 10 BSY RDY DF DSC DRQ COR IDX ERR 0V0 - - 0 -V The Set Feature command is to establish the following parameters which affect the execution of certain features as shown in below table. ABT will be set to 1 in the Error Register if the Feature register contains any undefined values. After power on reset or hard reset, the device is set to the following features as default. Write cache : Enable ECC bytes : 4 bytes Read look-ahead : Enable Reverting to power on defaults : Disable Address Offset mode : Disable Output Parameters To The Device Feature Destination code for this command 02H Enable write cache (Note.2) 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power-Up in Standby feature set 07H Power-Up in Standby feature set device spin-up 09H Enable Address Offset mode 42H Enable Automatic Acoustic Management feature set 44H 52 bytes of ECC apply on Read Long/Write Long commands 55H Disable read look-ahead feature 66H Disable reverting to power on defaults 82H Disable write cache 85H Disable Advanced Power Management (Note.3) 86H Disable Power-UP in Standby feature set 89H Disable Address Offset mode AAH Enable read look-ahead feature BBH 4 bytes of ECC apply on Read Long/Write Long commands C2H Disable Automatic Acoustic Management feature set CCH Enable reverting to power on defaults Note 1. When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. bits bits (7:3) (2:0) PIO Default Transfer Mode 00000 000 144/188