Hitachi HTS541680J9AT00 Specifications - Page 58

Registers

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Travelstar 5K160 (PATA) Hard Disk Drive Specification 11 Registers Addresses Functions CS0- CS1- DA2 DA1 DA0 READ (DIOR-) WRITE (DIOW-) N N X X X Data bus high imped*1 Not used Control block registers N A 0 X X Data bus high imped Not used N A 1 0 X Data bus high imped Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Features A N 0 1 0 Sector Count Sector Count A N 0 1 1 LBA Low LBA Low A N 0 1 1 LBA bits 0-7 LBA bits 0-7 A N 1 0 0 LBA Mid LBA Mid A N 1 0 0 LBA bits 8-15 LBA bits 8-15 A N 1 0 1 LBA High LBA High A N 1 0 1 LBA bits 16-23 LBA bits 16-23 A N 1 1 0 Device Device A N 1 1 0 LBA bits 24-27 LBA bits 24-27 A N 1 1 1 Status Command A A X X X Invalid address Invalid address *1 "imped" stands for "impedance" *2 "Mapping of registers in LBA mode Logic conventions : A = signal asserted N = signal negated X = does not matter which it is Figure 16 Register Set Communication to or from the device is through an I/O Register that routes the input or output data to or from registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-). The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status. Cylinder High/Low and Sector Number Register 11.1 Alternate Status Register Alternate Status Register 7 6 5 4 3 2 1 0 BSY RDY DF DSC DRQ COR IDX ERR Figure 17 Alternate Status Register This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See "11.13 Status Register" on page61 for the definition of the bits in this register. 11.2 Command register This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in "Figure 38 Command set" on page 90. All other registers required for the command must be set up before writing the Command Register. 58/188

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Travelstar 5K160 (PATA) Hard Disk Drive Specification
58
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11 Registers
Addresses
Functions
CS0-
CS1-
DA2
DA1
DA0
READ (DIOR-)
WRITE (DIOW-)
N
N
X
X
X
Data bus high imped*1
Not used
Control block registers
N
A
0
X
X
Data bus high imped
Not used
N
A
1
0
X
Data bus high imped
Not used
N
A
1
1
0
Alternate Status
Device Control
N
A
1
1
1
Device Address
Not used
Command block registers
A
N
0
0
0
Data
Data
A
N
0
0
1
Error
Features
A
N
0
1
0
Sector Count
Sector Count
A
N
0
1
1
LBA Low
LBA Low
A
N
0
1
1
LBA bits 0-7
LBA bits 0-7
A
N
1
0
0
LBA Mid
LBA Mid
A
N
1
0
0
LBA bits 8-15
LBA bits 8-15
A
N
1
0
1
LBA High
LBA High
A
N
1
0
1
LBA bits 16-23
LBA bits 16-23
A
N
1
1
0
Device
Device
A
N
1
1
0
LBA bits 24-27
LBA bits 24-27
A
N
1
1
1
Status
Command
A
A
X
X
X
Invalid address
Invalid address
*1 "imped" stands for "impedance"
*2 "Mapping of registers in LBA mode
Logic conventions : A = signal asserted
N = signal negated
X = does not matter which it is
Figure 16 Register Set
Communication to or from the device is through an I/O Register that routes the input or output data to or from
registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-).
The Command Block Registers are used for sending commands to the device or posting status from the device.
The Control Block Registers are used for device control and to post alternate status.
Cylinder High/Low and Sector Number Register
11.1
Alternate Status Register
Alternate Status Register
7
6
5
4
3
2
1
0
BSY
RDY
DF
DSC
DRQ
COR
IDX
ERR
Figure 17 Alternate Status Register
This register contains the same information as the Status Register. The only difference is that reading this register
does not imply interrupt acknowledge or clear a pending interrupt. See "11.13 Status Register" on page61 for the
definition of the bits in this register.
11.2
Command register
This register contains the command code being sent to the device. Command execution begins immediately after
this register is written. The command set is shown in "Figure 38 Command set" on page 90.
All other registers required for the command must be set up before writing the Command Register.