Intel D865GLC Manual - Page 77

This feature is displayed only if Extended Configuration is set to User Defined.

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Page 77 highlights

CPC Override SDRAM Timing Control (Note 1) • Auto (default) • Enabled • Disabled • Auto (default) • Manual - Aggressive • Manual - User Defined SDRAM RAS • 8 Active to • 7 Precharge (Note 4) • 6 (default) • 5 SDRAM CAS# • 2.0 Latency (Note 4) • 2.5 (default) • 3.0 SDRAM RAS# to • 4 CAS# Delay • 3 (default) (Note 4) • 2 SDRAM RAS# Precharge (Note 4) • 4 • 3 (default) • 2 Controls the CPC/1n rule mode Enabled allows the DRAM controller to attempt chip select assertions in two consecutive common clocks Auto = Timings will be programmed according to the memory detected. Manual - Aggressive = Selects most aggressive user-defined timings. Manual - User Defined = Allows manual override of detected SDRAM settings. Corresponds to tRAS Selects the number of clock cycles required to address a column in memory. Selects the number of clock cycles between addressing a row and addressing a column. Selects the length of time required before accessing a new row. Note: 1. This feature is displayed only if Extended Configuration is set to User Defined. 2. This option is displayed only if the installed processor has a 533 MHz system bus. 3. This option is displayed only if the installed processor has an 800 MHz system bus. 4. This feature is displayed only if SDRAM Timing Control is set to Manual - User Defined. D865GLC Motherboard Manual 76

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D865GLC Motherboard Manual
76
CPC Override
•
Auto (default)
•
Enabled
•
Disabled
Controls the CPC/1n rule mode
Enabled
allows the DRAM controller to attempt
chip select assertions in two consecutive common
clocks
SDRAM Timing
Control
(Note 1)
•
Auto (default)
•
Manual - Aggressive
•
Manual - User Defined
Auto
= Timings will be programmed according to
the memory detected.
Manual – Aggressive
= Selects most aggressive
user-defined timings.
Manual – User Defined
= Allows manual override
of detected SDRAM settings.
SDRAM RAS
Active to
Precharge (Note 4)
•
8
•
7
•
6 (default)
•
5
Corresponds to tRAS
SDRAM CAS#
Latency (Note 4)
•
2.0
•
2.5 (default)
•
3.0
Selects the number of clock cycles required to
address a column in memory.
SDRAM RAS# to
CAS# Delay
(Note 4)
•
4
•
3 (default)
•
2
Selects the number of clock cycles between
addressing a row and addressing a column.
SDRAM RAS#
Precharge
(Note 4)
•
4
•
3 (default)
•
2
Selects the length of time required before
accessing a new row.
Note:
1.
This feature is displayed only if Extended Configuration is set to User Defined.
2.
This option is displayed only if the installed processor has a 533 MHz system bus.
3.
This option is displayed only if the installed processor has an 800 MHz system bus.
4.
This feature is displayed only if SDRAM Timing Control is set to Manual – User Defined.