Casio QT 6000 Service Manual - Page 58

Block Diagram, External SH bus

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8-7-2. Block Diagram CPU UBC FPU Lower 32-bit data 32-bit address (instructions) 32-bit data (instructions) 32-bit address (data) 32-bit data (load) 32-bit data (store) 64-bit data (store) Upper 32-bit data I cache ITLB Cache and TLB controller UTLB O cache Peripheral data bus Peripheral address bus 29-bit address 32-bit data 32-bit data CPG INTC SCI (SCIF) RTC TMU PCIC (PCI)DMAC 32-bit PCI address/ data BSC DMAC Address 32-bit data Address 32-bit data 32-bit data External (SH) bus interface 26-bit SH bus address 32-bit SH bus data BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller FPU: Floating-point unit INTC: Interrupt controller ITLB: Instruction TLB (translation lookaside buffer) UTLB: Unified TLB (translation lookaside buffer) RTC: Realtime clock SCI: Serial communication interface SCIF: Serial communication interface with FIFO TMU: Timer unit UBC: User break controller PCIC: PCI bus controller - 56 -

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— 56 —
8-7-2. Block Diagram
Lower 32-bit data
64-bit data (store)
CPG
INTC
SCI
(SCIF)
RTC
TMU
External (SH) bus
interface
DMAC
32-bit data
29-bit address
32-bit data
Address
32-bit data
32-bit data
Upper 32-bit data
32-bit address (instructions)
32-bit data (instructions)
32-bit address (data)
Peripheral address bus
26-bit
SH bus
address
32-bit
PCI
address/
data
32-bit
SH bus
data
Peripheral data bus
UBC
32-bit data (store)
32-bit data (load)
CPU
I cache
O cache
ITLB
UTLB
Cache and
TLB
controller
FPU
BSC:
Bus state controller
CPG:
Clock pulse generator
DMAC:
Direct memory access controller
FPU:
Floating-point unit
INTC:
Interrupt controller
ITLB:
Instruction TLB (translation lookaside buffer)
UTLB:
Unified TLB (translation lookaside buffer)
RTC:
Realtime clock
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
TMU:
Timer unit
UBC:
User break controller
PCIC:
PCI bus controller
32-bit data
PCIC
BSC
Address
(PCI)DMAC