Casio QT 6000 Service Manual - Page 91

2 error point: Indicates the point on the memory where the operation instruction that causes the above general exception is located (program counter). However, an illegal address may be displayed depending on the exception code. 3 access adrs: Indicates the address that is accessed according to the operation instruction that causes the above general exception. However, the address is 0 (zero) and has no meaning if the access is not the cause. 4 Error Code Correspondence Table error no. error point access adrs Description of error 40 Location where error occurs Logical address of comparison source TLB address comparison results in address mismatch 60 Location where error occurs Logical address of error source TLB entry is invalid 80 Location where error occurs Logical address of error source Initial page write exception A0 Location where error occurs Logical address of error source TLB protection exception (read) C0 Location where error occurs Logical address of error source TLB protection exception (write) E0 Location where error occurs Address of read destination CPU address error (read) 100 Location where error occurs Address of write destination CPU address error (write) 180 Location where error occurs 0 Reservation instruction code exception 1A0 Location where error occurs 0 Slot illegal instruction exception 5 Causes of error occurrence (1) error no. 40: TLB address comparison results in address mismatch (2) error no. 60: TLB entry is invalid Description of phenomenon: The CPU performs a conversion from logical address to physical address when accessing the external memory. TLB is what caches that information. If an error occurs in the process of the caching, a general exception of the CPU occurs. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (3) error no. 80: Initial page write exception Description of phenomenon: This exception occurs if the address conversion table of the above TLB is illegally written. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (4) error no. A0: TLB protection exception (read) (5) error no. C0: TLB protection exception (write) Description of phenomenon: TLB is protected by setting access right. An access that violates the access right causes one of these exceptions to occur. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (6) error no. E0: CPU address error (read) (7) error no. 100: CPU address error (write) Description of phenomenon: This exception occurs if an illegal address is accessed (read or written). Possible causes: • An illegal address is accessed by software (a software bug). • The address to be accessed has changed due to insufficient charge of the backup battery for RAM. - 89 -