Casio QT 6000 Service Manual - Page 73

PIN NAME, DESCRIPTION, External Display Memory Interface, Flat Panel Interface

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PIN NAME I/O DESCRIPTION External Display Memory Interface MA [9:0] External Memory Address Bus. The video memory row and column addresses are multiplexed on these O lines. MD [63:0] I/O External Memory Data Bus ~WE O External Memory Write Strobe ~RAS O External Memory SDRAM Row Address Select ~CAS O External SGRAM Column Address Select ~CS0 External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB O memory ~DQM [7:0] External SGRAM I/O mask [7:0]. DQM [7:0] are byte specific. DQM0 masks MD [7:0], DQM1 masks MD O [15:8],Ö,and DQM7 masks MD [63:58]. DSF O External SGRAM Block write BA External SGRAM Bank Select. SDRAM has dual internal banks. Bank address defines to which bank the O current command is being applied. SDCK I/O External SGRAM clock. SDCK is driven by the memory clock. All SDRAM input signals are sampled on the positive edge of SDCK. SDCKEN External SGRAM clock enable. SDCKEN activates (HIGH) and deactivates (LOW) the SDCLK signal. I/O Deactivating the SDCK provides POWER-DOWN and SELF-REFRESH mode. ~ROMEN O ROM Enable Flat Panel Interface FDATA [23:0] O Flat Panel Data bit 23 to bit 0. Note: For SM712, the upper 12 bits [25:24] are multiplexed with ZV port, and the upper 12 bits [23:11] are dedicated for flat panel data LP/FHSYNC DSTN LCD: Line Pulse O TFT LCD: LCD Horizontal Sync FP/FVSYNC DSTN LCD: Frame Pulse O TFT LCD: LCD vertical sync M/ M-signal or Display Enable. This signal is used to indicate the active horizontal display time. DE FPR3E [7] is used to select O 1 = M-signal 0 = Display Enable FPSCLK O Flat Panel Shift Clock. This is the pixel clock for Flat Panel Data. FPEN Flat Panel Enable. This signal needs to become active after all panel voltages, clocks, and data are O supplied. This signal also needs to become inactive before any panel voltages or control signals are removed. FPEN is part of the VESA FPDI-1B specification. FPVDDEN O Flat Panel VDD Enable. This signal is used to control LCD logic power. VBIASEN O Flat Panel Voltage Bias Enable. This signal is used to control LCD Bias power. - 71 -

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— 71 —
PIN NAME
I/O
DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM
[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
O
External Memory Address Bus. The video memory row and column addresses are multiplexed on these
lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB
memory
External SGRAM I/O mask [7:0]. DQM [7:0] are byte specific. DQM0 masks MD [7:0], DQM1 masks MD
[15:8],Ö,and DQM7 masks MD [63:58].
External SGRAM Block write
External SGRAM Bank Select. SDRAM has dual internal banks. Bank address defines to which bank the
current command is being applied.
External SGRAM clock. SDCK is driven by the memory clock. All SDRAM input signals are sampled on the
positive edge of SDCK.
External SGRAM clock enable. SDCKEN activates (HIGH) and deactivates (LOW) the SDCLK signal.
Deactivating the SDCK provides POWER-DOWN and SELF-REFRESH mode.
ROM Enable
External Display Memory Interface
Flat Panel Interface
FDATA
[23:0]
LP/FHSYNC
FP/FVSYNC
M/
DE
FPSCLK
FPEN
FPVDDEN
VBIASEN
O
O
O
O
O
O
O
O
Flat Panel Data bit 23 to bit 0. Note: For SM712, the upper 12 bits [25:24] are multiplexed with ZV port, and
the upper 12 bits [23:11] are dedicated for flat panel data
DSTN LCD: Line Pulse
TFT LCD: LCD Horizontal Sync
DSTN LCD: Frame Pulse
TFT LCD: LCD vertical sync
M-signal or Display Enable. This signal is used to indicate the active horizontal display time.
FPR3E [7] is used to select
1 = M-signal
0 = Display Enable
Flat Panel Shift Clock. This is the pixel clock for Flat Panel Data.
Flat Panel Enable. This signal needs to become active after all panel voltages, clocks, and data are
supplied. This signal also needs to become inactive before any panel voltages or control signals are
removed. FPEN is part of the VESA FPDI-1B specification.
Flat Panel VDD Enable. This signal is used to control LCD logic power.
Flat Panel Voltage Bias Enable. This signal is used to control LCD Bias power.