Casio QT 6000 Service Manual - Page 77

Pin Function - how to change name on

Get Casio QT 6000 - 32 MB RAM PDF manuals and user guides View all Casio QT 6000 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 77 highlights

8-13-3. Pin Function PIN NAME D15-D8 I/O DESCRIPTION For 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or output data to and from an external memory. Otherwise, these pins are configured to be inputs only. I/O For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external microcontroller and memory. D7-D0 Birirectional data bus to input or output data and output status to and from an external microcontroller and I/O memory. WR I Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins. RD I Read pulse input pin. This pin pulses "L" when status or voice data is output to D15-D0 pins. Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read pulse when CS I this pin is "H". Voice data is input or output to and from D15-D0 pins when this pin is "H". Command is input to and status D/C I is output from D7-D0 pins when this pin is "L". BUSY O This pin outputs a "L" level during RECORDING, PLAYBACK or PAUSE. EMP "H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L" by O command input. "H" level indicates that more than half of the FIFO memory space is filled with data. During playback, voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active MID O "L" by command input. This pin outputs a synchro signal for voice data input/output when non-use of FIFO is selected. FUL/ DREQR "H" level indicates that FIFO memory is full of data. During playback, this pin is "H" and data cannot be written in FIFO memory. Active "H" can be changed to active "L" by command input. O When DMA transfer and stereo playback are selected, "H" level DREQR outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. CH/DACKR When stereo playback is selected and CH is "H", the EMP, MID or FUL pin outputs the status of right FIFO memory. When CH is "L", the EMP, MID or FUL pin outputs the status of left FIFO memory. Set this pin to I "L" during recording and monophonic playback. When DMA transfer and stereo playback are selected, DACKR is selected. In this case, input a DMA transfer acknowledge signal to DACKR. When DACKR is "L", the IOW signal is accepted. Active "L" can be changed to active "H" by command input. DREQL When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer. O When stereo playback is selected, "H" level DREQL outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. DACKL Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL is "L", IOR and IOW signals are accepted. When stereo playback is selected, input to DACKL a DMA transfer acknowl- I edge signal for left FIFO memory. Active "L" can be changed to active "H" by command input. If DMA transfer is not used, set this pin to "H" level. IOW Write pulse input pin to write external memory data to MSM9841 during DMA transfer. I If DMA transfer is not used, set this pin to "H" level. Read pulse input pin to read data of MSM9841 during DMA transfer. IOR I If DMA transfer is not used, set this pin to "H" level. ADSD I 16-bit serial data input pin when external ADC is used. If external ADC is not used, set this pin to "L" level. DASD O 16-bit serial data output pin when external DAC is used. SIOCK O Synchronizing clock for 16-bit serial data input/output when external ADC or DAC is used. - 75 -

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
— 75 —
8-13-3. Pin Function
PIN NAME
I/O
DESCRIPTION
D15-D8
D7-D0
WR
RD
CS
D/C
BUSY
EMP
MID
FUL/
DREQR
CH/DACKR
DREQL
DACKL
IOW
IOR
ADSD
DASD
SIOCK
I/O
I/O
I
I
I
I
O
O
O
O
I
O
I
I
I
I
O
O
For 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or
output data to and from an external memory. Otherwise, these pins are configured to be inputs only.
For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external
microcontroller and memory.
Birirectional data bus to input or output data and output status to and from an external microcontroller and
memory.
Write pulse input pin. This pin pulses “L” when command or voice data is input to D15-D0 pins.
Read pulse input pin. This pin pulses “L” when status or voice data is output to D15-D0 pins.
Accepts write pulse and read pulse when this pin is “L”. Does not accept write pulse and read pulse when
this pin is “H”.
Voice data is input or output to and from D15-D0 pins when this pin is “H”. Command is input to and status
is output from D7-D0 pins when this pin is “L”.
This pin outputs a “L” level during RECORDING, PLAYBACK or PAUSE.
“H” level indicates that there is no data in FIFO memory. Active “H” can be changed to active “L” by
command input.
“H” level indicates that more than half of the FIFO memory space is filled with data.
During playback, voice synthesis starts when MID changes to “H” level. Active “H” can be changed to active
“L” by command input. This pin outputs a synchro signal for voice data input/output when non-use of FIFO is
selected.
“H” level indicates that FIFO memory is full of data. During playback, this pin is “H” and data cannot be
written in FIFO memory. Active “H” can be changed to active “L” by command input.
When DMA transfer and stereo playback are selected, “H” level DREQR outputs a signal to request a DMA
transfer. Active “H” can be changed to active “L” by command input.
When stereo playback is selected and CH is “H”, the EMP, MID or FUL pin outputs the status of right FIFO
memory. When CH is “L”, the EMP, MID or FUL pin outputs the status of left FIFO memory. Set this pin to
“L” during recording and monophonic playback. When DMA transfer and stereo playback are selected,
DACKR is selected. In this case, input a DMA transfer acknowledge signal to DACKR. When DACKR is “L”,
the IOW signal is accepted. Active “L” can be changed to active “H” by command input.
When DMA transfer is selected, “H” level DREQL outputs a signal to request a DMA transfer.
When stereo playback is selected, “H” level DREQL outputs a signal to request a DMA transfer.
Active “H” can be changed to active “L” by command input.
Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL is “L”, IOR
and IOW signals are accepted. When stereo playback is selected, input to DACKL a DMA transfer acknowl-
edge signal for left FIFO memory. Active “L” can be changed to active “H” by command input. If DMA
transfer is not used, set this pin to “H” level.
Write pulse input pin to write external memory data to MSM9841 during DMA transfer.
If DMA transfer is not used, set this pin to “H” level.
Read pulse input pin to read data of MSM9841 during DMA transfer.
If DMA transfer is not used, set this pin to “H” level.
16-bit serial data input pin when external ADC is used. If external ADC is not used, set this pin to “L” level.
16-bit serial data output pin when external DAC is used.
Synchronizing clock for 16-bit serial data input/output when external ADC or DAC is used.